CN-122026875-A - Clock signal harmonic optimization circuit and method

CN122026875ACN 122026875 ACN122026875 ACN 122026875ACN-122026875-A

Abstract

The application provides a clock signal harmonic optimization circuit and a clock signal harmonic optimization method, and relates to the technical field of integrated circuit design. The circuit comprises a clock signal source, a driving buffer, an MCU, a duty ratio adjusting module and a control module, wherein the clock signal source is used for generating an original clock signal, the driving buffer is connected with the clock signal source and used for carrying out buffer amplification on the original clock signal and outputting a clock signal to be adjusted, the MCU is used for circularly acquiring target harmonic energy of the clock signal to be adjusted and generating a corresponding tuning instruction when the target harmonic energy is larger than a set value, the target harmonic energy refers to energy of N times of harmonic which affects a radio frequency system most, N is an integer larger than 1, and the duty ratio adjusting module is respectively connected with the driving buffer and the MCU and used for providing a control signal for the driving buffer according to the corresponding tuning instruction and adjusting the duty ratio of the clock signal to be adjusted so that the target harmonic energy is smaller than or equal to the set value. The scheme of the application has the advantages of low cost, high flexibility and capability of fine regulation and control.

Inventors

WANG CHENYANG
JIA CHENGWEI

Assignees

深圳市静远达智科技有限公司

Dates

Publication Date: 20260512
Application Date: 20260202

Claims (10)

1. A clock signal harmonic optimization circuit, the circuit comprising: A clock signal source for generating an original clock signal; the driving buffer is connected with the clock signal source and used for carrying out buffer amplification on the original clock signal and outputting a clock signal to be modulated; The MCU circularly acquires target harmonic energy of the clock signal to be modulated and generates a corresponding tuning instruction when the target harmonic energy is larger than a set value, wherein the target harmonic energy refers to energy of N harmonics which have the greatest influence on a radio frequency system, and N is an integer larger than 1; And the duty ratio adjusting module is respectively connected with the driving buffer and the MCU, and is used for providing a control signal for the driving buffer according to the corresponding tuning instruction and adjusting the duty ratio of the clock signal to be tuned so as to enable the target harmonic energy to be smaller than or equal to a set value.
2. The clock signal harmonic optimization circuit of claim 1, wherein the drive buffer comprises a first pull-up P-type tube and a first pull-down N-type tube, the first pull-up P-type tube is connected with the first pull-down N-type tube and forms a push-pull structure, the control signal comprises a first bias voltage and/or a second bias voltage, the first bias voltage is applied to a body end of the first pull-up P-type tube, the second bias voltage is applied to the body end of the first pull-down N-type tube, and the original clock signal is applied to gates of the first pull-up P-type tube and the first pull-down N-type tube.
3. The clock signal harmonic optimization circuit of claim 1, wherein the drive buffer comprises a first pull-up P-type tube, a second pull-up P-type tube, a first pull-down N-type tube, and a second pull-down N-type tube, the first pull-up P-type tube, the second pull-up P-type tube, the first pull-down N-type tube, and the second pull-down N-type tube being connected and configured in a push-pull configuration, the control signal comprising a first bias voltage and/or a second bias voltage, the first bias voltage being applied to a gate of the second pull-up P-type tube, the second bias voltage being applied to a gate of the second pull-down N-type tube, the original clock signal being applied to gates of the first pull-up P-type tube and the first pull-down N-type tube.
4. A clock signal harmonic optimisation circuit as claimed in claim 2 or 3 wherein the tuning instructions comprise a digital control code and the duty cycle adjustment module is arranged to convert the digital control code to an analogue first bias voltage and/or second bias voltage.
5. A method of clock signal harmonic optimization, for use in an MCU in a clock signal harmonic optimization circuit as claimed in any one of claims 1 to 4, the method comprising: Acquiring target harmonic energy of a clock signal to be modulated; When the target harmonic energy is larger than a set value, a corresponding tuning instruction is generated, and the duty ratio adjusting module is controlled to provide a control signal for the driving buffer according to the corresponding tuning instruction so as to adjust the duty ratio of the clock signal to be adjusted; repeating the steps of acquiring target harmonic energy of the clock signal to be tuned and generating a tuning instruction until the target harmonic energy is less than or equal to a set value.
6. The method of claim 5, wherein when the target harmonic energy is energy of a single type of harmonic, the steps of acquiring the target harmonic energy of the clock signal to be tuned and generating the tuning instruction are repeatedly performed until the target harmonic energy is less than or equal to a set value, comprising: The steps of acquiring the target harmonic energy of the clock signal to be tuned and generating the tuning instruction are repeatedly performed until the target harmonic energy reaches a minimum value.
7. The method of clock signal harmonic optimization of claim 5 wherein when the target harmonic energy comprises a first target harmonic energy and a second target harmonic energy, repeating the steps of obtaining the target harmonic energy of the clock signal to be tuned and generating tuning instructions until the target harmonic energy is less than or equal to a set point comprises: repeating the steps of acquiring the target harmonic energy of the clock signal to be tuned and generating a tuning instruction aiming at the first target harmonic energy until the first target harmonic energy reaches the minimum value, and determining a corresponding first duty ratio; Repeating the steps of acquiring the target harmonic energy of the clock signal to be tuned and generating a tuning instruction aiming at the second target harmonic energy until the second target harmonic energy reaches the minimum value, and determining a corresponding second duty ratio; The steps of acquiring target harmonic energy of the clock signal to be tuned and generating tuning instructions are repeatedly performed until the target harmonic energy is less than or equal to a set value, and the method further comprises: And scanning the first duty ratio and the second duty ratio according to a set step length, and taking the duty ratio corresponding to the minimum sum of the first target harmonic energy and the second target harmonic energy as the duty ratio of the final output clock signal.
8. The method of claim 7, wherein when the target harmonic energy is greater than a set value, generating a corresponding tuning instruction according to a first adjustment step, the set step being a second adjustment step, the second adjustment step being smaller than the first adjustment step.
9. The method of clock signal harmonic optimization of claim 5 wherein the steps of repeatedly performing the steps of obtaining target harmonic energy of the clock signal to be tuned and generating tuning instructions until the target harmonic energy is less than or equal to a set point comprises: the duty ratio of the clock signal to be modulated is adjusted according to a third adjustment step length, and a corresponding duty ratio interval when the target harmonic energy reaches the minimum value is determined; The duty ratio of the clock signal to be modulated is adjusted in the duty ratio interval according to a fourth adjustment step length, and the corresponding target duty ratio when the target harmonic energy reaches the minimum value is determined, wherein the fourth adjustment step length is smaller than the third adjustment step length; and generating a corresponding tuning instruction according to the target duty ratio.
10. The method of clock signal harmonic optimization of claim 5 wherein the step of generating corresponding tuning instructions when the target harmonic energy is greater than a set point comprises: when the target harmonic energy is greater than a set value, a tuning instruction having 50% as an initial duty cycle is generated.

Description

Clock signal harmonic optimization circuit and method Technical Field The application relates to the technical field of integrated circuit design, in particular to a clock signal harmonic optimization circuit and a clock signal harmonic optimization method. Background In modern high-speed digital electronic systems, clock signals play a critical role, and the waveform quality directly affects the stability and reliability of the whole system. Ideally, the clock signal should be a perfect square wave with symmetrical rise and fall times and an accurate 50% duty cycle. However, in practical operation, due to factors such as non-ideal characteristics of the device, process deviation or load mismatch, distortion often exists in the output waveform, and such non-ideal periodic signals may appear as a series of discrete frequency components in the frequency domain, including components of integer multiples of the fundamental frequency, and these high frequency components are called harmonics (Harmonic Component). Specifically, any periodic non-sinusoidal signal can be decomposed by fourier transform into a superposition of one fundamental sine wave and multiple higher order harmonics. Taking a typical square wave as an example, its spectrum contains not only fundamental frequency components but also odd harmonics (e.g., 3 rd order, 5 th order, 7 th order, etc.), and when the duty cycle deviates from 50%, significant even harmonics (e.g., 2 th order, 4 th order, 6 th order, etc.) are introduced. Although the amplitude of these harmonic energies is usually lower than the fundamental frequency, they can still cause serious interference in certain sensitive frequency bands, especially in high-speed integrated circuits, which are easily coupled to adjacent signal lines to cause crosstalk or propagate through power/ground networks to cause electromagnetic radiation to exceed the standard, affecting the normal operation of other functional modules. It should be noted that as the operating frequency of electronic devices continues to increase, the requirements of the system for electromagnetic compatibility (Electromagnetic Compatibility, EMC) are also becoming increasingly stringent. If a particular number of harmonics fall within a critical reception frequency band, such as the operating frequency band of a wireless communication module, this may lead to increased bit error rates and even communication disruption. Therefore, how to effectively suppress these harmful harmonics, especially for those individual higher harmonics that have the greatest influence, has become an important issue in high-speed circuit design. Current methods of suppressing clock harmonic interference include using spread spectrum clocks, adding shields, optimizing PCB layout, using filters, etc. These approaches either add to the cost and complexity of the system or lack flexibility in the design and tuning stages, failing to perform fine, specific harmonic optimization. In summary, the existing scheme for suppressing clock harmonic interference has the problems of high cost, poor flexibility and incapability of fine adjustment and control. Disclosure of Invention The application aims to provide a clock signal harmonic optimization circuit and a clock signal harmonic optimization method, which are used for solving the problems of high cost, poor flexibility and incapability of fine regulation and control in a scheme for inhibiting clock harmonic interference in the prior art. In order to achieve the above object, the technical scheme adopted by the embodiment of the application is as follows: In one aspect, an embodiment of the present application provides a clock signal harmonic optimization circuit, including: A clock signal source for generating an original clock signal; the driving buffer is connected with the clock signal source and used for carrying out buffer amplification on the original clock signal and outputting a clock signal to be modulated; The MCU circularly acquires target harmonic energy of the clock signal to be modulated and generates a corresponding tuning instruction when the target harmonic energy is larger than a set value, wherein the target harmonic energy refers to energy of N harmonics which have the greatest influence on a radio frequency system, and N is an integer larger than 1; And the duty ratio adjusting module is respectively connected with the driving buffer and the MCU, and is used for providing a control signal for the driving buffer according to the corresponding tuning instruction and adjusting the duty ratio of the clock signal to be tuned so as to enable the target harmonic energy to be smaller than or equal to a set value. Optionally, the driving buffer includes a first pull-up P-type tube and a first pull-down N-type tube, the first pull-up P-type tube is connected with the first pull-down N-type tube and forms a push-pull structure, the control signal includes a first bias voltage and/or a second bias