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CN-122026884-A - Semiconductor device and electronic control system

CN122026884ACN 122026884 ACN122026884 ACN 122026884ACN-122026884-A

Abstract

The present disclosure relates to semiconductor devices and electronic control systems. The discharge transistor is formed on the semiconductor substrate, and when controlled to an on state, the power transistor is controlled to an off state by shorting the gate of the power transistor and a reference node. The reverse current detection circuit detects generation of a reverse current from the power output terminal toward the power supply terminal, and asserts a reverse current detection signal in a period in which the reverse current is generated. The switch control circuit controls the first switch to an on state and the second switch to an off state during an inversion period of the reverse current detection signal, and controls the first switch to an off state and the second switch to an on state during an assertion period of the reverse current detection signal.

Inventors

  • NAKAHARA AKIHIRO

Assignees

  • 瑞萨电子株式会社

Dates

Publication Date
20260512
Application Date
20251107
Priority Date
20241112

Claims (14)

  1. 1. A semiconductor device, comprising: An output transistor formed on the semiconductor substrate and connected between the power supply terminal and the power output terminal, and configured to supply power to a load connected to the power output terminal when controlled to be in a conductive state; a first switch configured to connect the power output terminal to a reference node; A second switch configured to connect the power supply terminal to the reference node; a first control transistor formed on the semiconductor substrate and configured to control the output transistor to an off state by shorting a gate of the output transistor and the reference node when controlled to the on state; A reverse current detection circuit configured to detect generation of a reverse current from the power output terminal toward the power supply terminal and to assert a reverse current detection signal in a period in which the reverse current is generated, and And a switch control circuit configured to control the first switch to the on state and the second switch to the off state in a reversal period of the reverse current detection signal, and to control the first switch to the off state and the second switch to the on state in an assertion period of the reverse current detection signal.
  2. 2. The semiconductor device according to claim 1, Wherein the output transistor includes an n-channel MOSFET having the power output terminal and the power supply terminal as a source and a drain respectively, Wherein the first switch comprises a first FET, the first FET being an n-channel MOSFET, and Wherein the second switch comprises a second FET, the second FET being a p-channel MOSFET.
  3. 3. The semiconductor device of claim 2, further comprising: A fourth FET and a fifth FET connected in series between the power output terminal and the reference node, connected in parallel with the first FET, and both being n-channel MOSFETs, Wherein in the fourth FET one of a source and a drain is connected to the reference node, the other is connected to an intermediate node, a gate is connected to the intermediate node, Wherein in the fifth FET, one of a source and a drain is connected to the intermediate node, and the other is connected to the power output terminal, Wherein the first FET and the fifth FET are commonly controlled to be turned on and off by the switch control circuit, and Wherein back gates of the first FET, the fourth FET, and the fifth FET are connected to the intermediate node.
  4. 4. The semiconductor device of claim 1, further comprising: an on/off control circuit configured to control on/off of the first control transistor based on an on/off control signal for externally indicating on/off of the output transistor, and A charge pump circuit configured to generate a boosted voltage that is higher than a power supply voltage applied to the power supply terminal in an active state.
  5. 5. The semiconductor device of claim 4, further comprising: a third switch connected in parallel with the first switch, Wherein the on/off control circuit further controls an active state and an inactive state of the charge pump circuit and on/off of the third switch, Wherein the switch control circuit controls the first switch to the on state using the boost voltage, and Wherein when the turn-off of the output transistor is indicated by the on/off control signal, the on/off control circuit controls the charge pump circuit in the active state to an inactive state by a predetermined delay time, and controls the third switch to the on state using the power supply voltage.
  6. 6. The semiconductor device according to claim 5, Wherein the output transistor includes an n-channel MOSFET having the power output terminal and the power supply terminal as a source and a drain respectively, Wherein the first switch comprises a first FET, the first FET being an n-channel MOSFET, Wherein the second switch comprises a second FET, the second FET being a p-channel MOSFET, and Wherein the third switch comprises a third FET, the third FET being an n-channel MOSFET.
  7. 7. The semiconductor device of claim 4, further comprising: A second control transistor formed on the semiconductor substrate and configured to control the output transistor to the off state by shorting a gate of the output transistor to the reference node in response to a predetermined abnormality detection.
  8. 8. The semiconductor device according to claim 1, Wherein the output transistor includes a vertical n-channel MOSFET having a back surface of the semiconductor substrate as a drain and the power output terminal and the power supply terminal as a source and a drain, respectively, Wherein the first control transistor comprises a horizontal n-channel MOSFET having the reference node and the gate of the output transistor as source and drain respectively, Wherein an NPN parasitic bipolar transistor is formed in the first control transistor, and Wherein the parasitic bipolar transistor operates with a back gate of the first control transistor and a source connected to the back gate as bases, and with one of the drain of the first control transistor and the back surface of the semiconductor substrate as an emitter and the other as a collector.
  9. 9. The semiconductor device according to claim 1, wherein The reverse current detection circuit includes a comparator that compares a magnitude of a power supply voltage applied to the power supply terminal with a magnitude of an output voltage generated at the power output terminal.
  10. 10. An electronic control system, comprising: A power supply terminal to which a power supply voltage is supplied; a power output terminal to which a load is connected; A semiconductor device configured to supply power to the load, and A control device configured to control the semiconductor device; wherein the semiconductor device includes: An output transistor formed on a semiconductor substrate, connected between the power supply terminal and the power output terminal, and configured to supply power to the load when controlled to be in an on state; a first switch configured to connect the power output terminal to a reference node; A second switch configured to connect the power supply terminal to the reference node; a first control transistor formed on the semiconductor substrate and configured to control the output transistor to an off state by shorting a gate of the output transistor and the reference node when controlled to the on state; A reverse current detection circuit configured to detect generation of a reverse current from the power output terminal toward the power supply terminal and to assert a reverse current detection signal in a period in which the reverse current is generated, and A switch control circuit configured to control the first switch to the on state and the second switch to the off state in a reversal period of the reverse current detection signal, and to control the first switch to the off state and the second switch to the on state in an assertion period of the reverse current detection signal; Wherein the control device outputs an on/off control signal for instructing on/off of the output transistor to the semiconductor device.
  11. 11. The electronic control system of claim 10, Wherein the output transistor includes an n-channel MOSFET having the power output terminal and the power supply terminal as a source and a drain respectively, Wherein the first switch comprises a first FET, the first FET being an n-channel MOSFET, and Wherein the second switch comprises a second FET, the second FET being a p-channel MOSFET.
  12. 12. The electronic control system of claim 11, Wherein the semiconductor device further includes a fourth FET and a fifth FET connected in series between the power output terminal and the reference node, connected in parallel with the first FET, and both the fourth FET and the fifth FET are n-channel MOSFETs, Wherein in the fourth FET one of a source and a drain is connected to the reference node, the other is connected to an intermediate node, a gate is connected to the intermediate node, Wherein in the fifth FET, one of a source and a drain is connected to the intermediate node, and the other is connected to the power output terminal, Wherein the first FET and the fifth FET are commonly controlled to be turned on and off by the switch control circuit, and Wherein back gates of the first FET, the fourth FET, and the fifth FET are connected to the intermediate node.
  13. 13. The electronic control system of claim 10, Wherein the semiconductor device further comprises: an on/off control circuit configured to control on/off of the first control transistor based on an on/off control signal for externally indicating on/off of the output transistor, and A charge pump circuit configured to generate a boosted voltage that is higher than a power supply voltage applied to the power supply terminal in an active state.
  14. 14. The electronic control system of claim 13, Wherein the semiconductor device further comprises a third switch connected in parallel with the first switch, Wherein the on/off control circuit further controls an active state and an inactive state of the charge pump circuit and on/off of the third switch, Wherein the switch control circuit controls the first switch to the on state using the boost voltage, and Wherein when the turn-off of the output transistor is indicated by the on/off control signal, the on/off control circuit controls the charge pump circuit in the active state to an inactive state by a predetermined delay time, and controls the third switch to the on state using the power supply voltage.

Description

Semiconductor device and electronic control system Cross Reference to Related Applications The entire disclosure of Japanese patent application No. 2024-197335 filed 11/12/2024, including the specification, drawings and abstract, is incorporated herein by reference. Technical Field The present invention relates to a semiconductor device and an electronic control system, and for example, relates to a semiconductor device that supplies power to a load connected to the outside and an electronic control system on which the semiconductor device is mounted. Background Techniques listed below are disclosed. [ Patent document 1] Japanese patent application laid-open No. 2018-11117 Patent document 1 discloses a semiconductor device capable of preventing a protection transistor from malfunctioning when a reverse current is generated. The semiconductor device includes a power transistor and a protection circuit that uses the protection transistor to form a short between a gate and a source of the power transistor when a load is shorted. The protection circuit detects a load short circuit by a combination of a determination of the output voltage of the power transistor and a time determination by a timer. In the protection transistor, a parasitic bipolar transistor is formed that turns on when a reverse current flows through the power transistor. Here, the protection circuit is configured to detect the load short circuit without error when the reverse current is eliminated by controlling the timer based on the determination result of the output voltage. Disclosure of Invention For example, as disclosed in patent document 1, there is known a semiconductor device including a power transistor and a protection transistor that forms a short between a gate and a source of the power transistor when controlled to be in an on state. In a power transistor that supplies power to a load, when an output voltage is higher than a power supply voltage, a reverse current is generated from the load to a power supply terminal. Such a reverse current occurs, for example, when a capacitive load, an inductive load, or the like is driven. As another example, when the load is a generator, the ripple current generated by rectification may also be a reverse current. This reverse current flows through the body diode of the power transistor when the power transistor is in an off state. Here, a parasitic bipolar transistor that is turned on when a reverse current is generated may be formed in the protection transistor. The parasitic bipolar transistor in the on state connects the gate of the power transistor to the supply voltage. On the other hand, in order to turn on the power transistor in the off state, a boosted voltage higher than the power supply voltage needs to be applied to the gate. However, when the parasitic bipolar transistor is in an on state, it may be difficult to apply a boost voltage to the gate of the power transistor due to the above-described connection to the power supply voltage. That is, during the period in which the reverse current is generated, there is a possibility that the power transistor cannot be turned on. In view of these circumstances, embodiments to be described below have been made, and other problems and novel features will be apparent from the description and drawings of the present specification. The semiconductor device according to the embodiment includes an output transistor, a first switch, a second switch, a first control transistor, a reverse current detection circuit, and a switch control circuit. The output transistor is formed on the semiconductor substrate, is connected between the power supply terminal and the power output terminal, and supplies power to a load connected to the power output terminal when controlled to be in an on state. The first switch connects the power output terminal to the reference node. The second switch connects the power supply terminal to the reference node. The first control transistor is formed on the semiconductor substrate, and when controlled to an on state, controls the output transistor to an off state by shorting the gate of the output transistor and a reference node. The reverse current detection circuit detects generation of a reverse current from the power output terminal to the power supply terminal, and makes a reverse current detection signal assert (assent) in a period in which the reverse current is generated. The switch control circuit controls the first switch to an on state and the second switch to an off state during an inversion period of the reverse current detection signal, and controls the first switch to an off state and the second switch to an on state during an assertion period of the reverse current detection signal. According to this embodiment, even in a period in which a reverse current is generated from the load to the output transistor, the output transistor can be turned on. Drawings Fig. 1 is a circuit diagram showing a configuration