CN-122026889-A - SRAM-based low-overhead high-robustness four-point flip-flop reinforcement latch

CN122026889ACN 122026889 ACN122026889 ACN 122026889ACN-122026889-A

Abstract

The invention relates to the technical field of latches, and discloses a low-overhead high-robustness four-point flip reinforcement latch based on SRAM, which comprises an input module, a storage module and an output module, wherein the input module comprises transmission gates TG 1-TG 5, transmission pipes PT 1-PT 8, the storage module comprises LOHR1, LOHR2, LOHR3 and LOHR4, the nodes N1-N16 are formed by cross coupling between LOHR1, LOHR2, LOHR3 and LOHR4, and the output module comprises four input clock control C units C1. The invention can completely tolerate four-node overturn inside, has higher four-point overturn self-recovery rate, higher reinforcement performance and reliability, reduces area overhead by using the SRAM unit, has lower power consumption, has low delay by using only one transmission gate from an input end to an output end in a transparent mode, and can be widely applied to the fields with high requirements on the reliability of latches, such as aerospace, medical treatment and the like.

Inventors

HUANG ZHENGFENG
YAN AIBIN
ZHANG YUQING
YANG JIAFENG
Zhou Tingan
PANG KAIWEN
CHEN JUNYI
SUN MENG
LU YINGCHUN
LIU BO

Assignees

合肥工业大学

Dates

Publication Date: 20260512
Application Date: 20260119

Claims (8)

1. A SRAM-based low overhead high robustness four-point flip-flop reinforcement latch comprising: The input module comprises transmission gates TG 1-TG 5, transmission pipes PT 1-PT 8; The storage module comprises LOHR, LOHR, LOHR and LOHR4, and the LOHR, LOHR2, LOHR, 3 and LOHR4 are cross-coupled to form nodes N1-N16; The output module comprises a four-input clock control C unit C1; Node N1 is connected with transmission gate TG2, node N2 is connected with transmission tube PT5, node N3 is connected with transmission tube PT1, node N5 is connected with transmission gate TG3, node N6 is connected with transmission tube PT6, node N7 is connected with transmission tube PT2, node N9 is connected with transmission gate TG4, node N10 is connected with transmission tube PT7, node N11 is connected with transmission tube PT3, node N13 is connected with transmission gate TG5, node N14 is connected with transmission tube PT8, node N15 is connected with transmission tube PT4, When the logic value of CLK of the transmission gates TG 1-TG 5 and the transmission tubes PT 1-PT 8 is 1 and the logic value of CLKB is 0, the latch is in a transparent period, the transmission gates TG 1-TG 5, the transmission tubes PT 1-PT 8 are conducted, the input signals D are simultaneously transmitted to the inside of the latch, and the logic value of the output node Q of the transmission gate TG1 is directly updated by the transmission gate TG 1; When the logic value of CLK of the transmission gates TG 1-TG 5, the transmission pipes PT 1-PT 8 is 0, and the logic value of CLKB is 1, the latch is in the hold period, the transmission gates TG 1-TG 5, the transmission pipes PT 1-PT 8 are turned off, and the data is latched in the storage module and transmitted to the output through the four-input clock control C unit C1.
2. The SRAM-based low overhead high robustness four-point flip-flop reinforcement latch of claim 1, wherein said LOHR comprises PMOS transistors MP 1-MP 6 and NMOS transistors MN 1-MN 8; LOHR2 include PMOS transistors MP 7-MP 12 and NMOS transistors MN 9-MN 16; LOHR3 includes PMOS transistors MP 13-MP 18 and NMOS transistors MN 17-MN 24; LOHR4 includes PMOS transistors MP 19-MP 24 and NMOS transistors MN 25-MN 32; Node N1 is connected to MP2, MP6, MP21, MN1 and MN 29; node N2 is connected to MP1, MN2, MN3, MN6 and MN 15; Node N3 is connected to MP5, MN3, MN5, MN6, MN8 and MN 12; Node N4 is connected to MP2, MP6, MP16, MN18 and MN 8; Node N5 is connected to MP3, MP8, MP12, MN5 and MN 9; Node N6 is connected to MP7, MN9, MN10, MN11, MN14 and MN 23; Node N7 is connected to MP11, MN13, MN14, MN16, and MN 20; node N8 is connected to MP7, MP12, MN16, MP22 and MN 26; node N9 is connected to MP14, MN17, MP9, MN13, and MP 18; Node N10 is connected to MP13, MN17, MN18, MN19, MN22, and MN 31; node N11 is connected to MN19, MN21, MN22, MN24, MN28 and MP 17; node N12 is connected to MP18, MN24, MP14, MP4 and MN 2; node N13 is connected to MP20, MN25, MP15, MN21, and MP 24; Node N14 is connected to MP19, MN25, MN7, MN26, MN27 and MN 30; node N15 is connected to MN27, MN29, MN30, MN32, MP23 and MN 4; Node N16 is connected to MP24, MN32, MP20, MN10, and MP 10.
3. The low-overhead high-robustness four-point flip-flop reinforcement latch according to claim 1, wherein an output end of the transmission gate TG1 is connected with an output end Q of the output module, an output end of the transmission gate TG2 is connected with a node N1, an output end of the transmission gate TG3 is connected with a node N5, an output end of the transmission gate TG4 is connected with a node N9, an output end of the transmission gate TG5 is connected with a node N13, an output end of the transmission pipe PT1 is connected with a node N3, an output end of the transmission pipe PT2 is connected with a node N7, an output end of the transmission pipe PT3 is connected with a node N11, an output end of the transmission pipe PT4 is connected with a node N15, an output end of the transmission pipe PT5 is connected with a node N2, an output end of the transmission pipe PT6 is connected with a node N6, an output end of the transmission pipe PT7 is connected with a node N10, and an output end of the transmission pipe PT8 is connected with a node N14.
4. The SRAM-based low overhead, high robustness four-point flip-flop reinforcement latch of claim 1, wherein said node N4, node N8, node N12 and node N16 are connected with a four-input clocked C cell C1.
5. The low-overhead high-robustness four-point flip-flop reinforcement latch of claim 2, wherein the drain connections of MP2 and MN1 are used as node N1, the drain connections of MN2 and MN3 are used as node N2, the drain connections of MN5 and MN6 are used as node N3, the drain connections of MP6 and MN8 are used as node N4, the drain of MP1 is connected with the source of MP2, MP3 is connected with the drain of MN2, the source of MN3 is connected with the drain of MN4, MP4 is connected with the drain of MN5, the source of MN6 is connected with the drain of MN7, the drain of MP5 is connected with the source of MP6, the gate of MP1, the gate of MN6 is connected with the drain of MN3, the gate of MP4, the gate of MP2 is connected with the drain of MP6, the gate of MP5 is connected with the drain of MP2, the gate of MP3, the gate of MN8 is connected with the drain of MP6, the gate of MP1, the gate of MN4 is connected with the drain of MP3, the drain of MP4 is connected with the source of MP 35, the drain of MP1, the gate of MN4 and the source of MN4 are connected with the drain of 35, the drain of 35 and 35.
6. The low-overhead high-robustness four-point flip-flop reinforcement latch based on SRAM of claim 1, wherein said transmission gate TG1 comprises a PMOS transistor-7 and an NMOS transistor-9, the sources of the PMOS transistor-7 and the NMOS transistor-9 are connected as inputs of the transmission gate, the drains of the PMOS transistor-7 and the NMOS transistor-9 are connected as outputs of the transmission gate, the gate of the PMOS transistor-7 is connected with a complementary clock signal CLKB, the gate of the NMOS transistor-9 is connected with a clock signal CLK, and the transmission gate TG1 is in accordance with the structures of the transmission gate TG2, the transmission gate TG3, the transmission gate TG4 and the transmission gate TG 5.
7. The low-overhead high-robustness four-point flip-flop reinforcement latch based on SRAM of claim 1, wherein said pass transistor PT1 comprises an NMOS transistor-10, a source of the NMOS transistor-10 being an input of the pass transistor, a drain of the NMOS transistor-10 being an output of the pass transistor, a gate of the NMOS transistor-10 being connected to a clock signal CLK, the pass transistor PT1 being in structural correspondence with pass transistors PT2, PT3, PT4, PT5, PT6, PT7 and PT 8.
8. The low-overhead high-robustness four-point flip-flop reinforced latch of claim 1, wherein said four-input clocked C-cell C1 comprises a PMOS transistor-8, a PMOS transistor-9, a PMOS transistor-10, a PMOS transistor-11, a PMOS transistor-12, an NMOS transistor-11, an NMOS transistor-12, an NMOS transistor-13, an NMOS transistor-14 and an NMOS transistor-15, wherein the drain of the PMOS transistor-8 is connected to the source of the PMOS transistor-9, the drain of the PMOS transistor-9 is connected to the source of the PMOS transistor-10, the drain of the PMOS transistor-10 is connected to the source of the PMOS transistor-11, the source of the PMOS transistor-11 is connected to the drain of the NMOS transistor-12, the source of the NMOS transistor-13 is connected to the drain of the NMOS transistor-13, the source of the NMOS transistor-13 is connected to the drain of the NMOS transistor-14, the drain of the NMOS transistor-14 is connected to the drain of the NMOS transistor-14, the gate of the PMOS transistor-14 is connected to the source of the PMOS transistor-11, the drain of the PMOS transistor-15 is connected to the source of the PMOS transistor-12, the drain of the PMOS transistor-15 is connected to the drain of the PMOS transistor-11 is connected to the drain of the NMOS transistor-12, the drain of the PMOS transistor-12 is connected to the drain of the NMOS transistor-12 is connected to the drain of the NMOS transistor-12, the gate of the PMOS transistor-12 is connected to the clock signal CLK and the gate of the NMOS transistor-11 is connected to the complementary clock signal CLKB.

Description

SRAM-based low-overhead high-robustness four-point flip-flop reinforcement latch Technical Field The invention relates to the technical field of latches, in particular to a low-overhead high-robustness four-point flip-flop reinforced latch based on SRAM. Background With the continuous progress of CMOS processes, the feature size of integrated circuits has reached the nanometer level, significantly improving the integration level and performance of integrated circuits and systems. However, with smaller and smaller transistor sizes, the critical charge amount of the circuit node is also continuously decreasing. Thus, CMOS devices are increasingly susceptible to soft errors. In a high-radiation scene, the silicon substrate is easily impacted by high-energy particles such as alpha particles, heavy ions, neutrons and the like, so that electron-hole pairs are excited. When these carriers drift into the active region of the device and are trapped by the sensitive nodes, if the collected charge quantity breaks through the critical threshold, the node logic value will flip, causing abnormal voltage jumps, which is defined as single node flip (SNU), which may cause transient faults and destroy the normal logic function of the circuit. With the development of the nanoscale CMOS process towards smaller size and higher integration, the impact effect of single high-energy particles is further amplified, namely, particle energy can be collected by active areas of a plurality of adjacent devices at the same time, so that two, three or even four adjacent nodes are affected, and double-node inversion (DNU), triple-node inversion (TNU) and quad-node inversion (QNU) are respectively caused, and the phenomena are collectively called multi-node inversion (MNU). The existing reinforcement latch has different levels of compromise in terms of delay, power consumption, area cost, fault tolerance performance and the like, has small circuit cost but poor fault tolerance performance, has good fault tolerance performance but large circuit cost, so that a multi-point reinforcement latch which is better balanced in terms of circuit cost and fault tolerance performance is further required to be designed, and therefore the SRAM-based four-point flip reinforcement latch with low cost and high robustness is provided. Disclosure of Invention In order to solve the technical problems in the prior art, the invention provides a low-overhead high-robustness four-point flip-flop reinforcement latch based on SRAM. The invention adopts the following technical scheme that the low-overhead high-robustness four-point flip-flop reinforcement latch based on the SRAM comprises: The input module comprises transmission gates TG 1-TG 5, transmission pipes PT 1-PT 8; The storage module comprises LOHR, LOHR, LOHR and LOHR4, and the LOHR, LOHR2, LOHR, 3 and LOHR4 are cross-coupled to form nodes N1-N16; The output module comprises a four-input clock control C unit C1; Node N1 is connected with transmission gate TG2, node N2 is connected with transmission tube PT5, node N3 is connected with transmission tube PT1, node N5 is connected with transmission gate TG3, node N6 is connected with transmission tube PT6, node N7 is connected with transmission tube PT2, node N9 is connected with transmission gate TG4, node N10 is connected with transmission tube PT7, node N11 is connected with transmission tube PT3, node N13 is connected with transmission gate TG5, node N14 is connected with transmission tube PT8, node N15 is connected with transmission tube PT4, When the logic value of CLK of the transmission gates TG 1-TG 5 and the transmission tubes PT 1-PT 8 is 1 and the logic value of CLKB is 0, the latch is in a transparent period, the transmission gates TG 1-TG 5, the transmission tubes PT 1-PT 8 are conducted, the input signals D are simultaneously transmitted to the inside of the latch, and the logic value of the output node Q of the transmission gate TG1 is directly updated by the transmission gate TG 1; When the logic value of CLK of the transmission gates TG 1-TG 5, the transmission pipes PT 1-PT 8 is 0, and the logic value of CLKB is 1, the latch is in the hold period, the transmission gates TG 1-TG 5, the transmission pipes PT 1-PT 8 are turned off, and the data is latched in the storage module and transmitted to the output through the four-input clock control C unit C1. As a further improvement of the above scheme, LOHR includes PMOS transistors MP 1-MP 6 and NMOS transistors MN 1-MN 8; LOHR2 include PMOS transistors MP 7-MP 12 and NMOS transistors MN 9-MN 16; LOHR3 includes PMOS transistors MP 13-MP 18 and NMOS transistors MN 17-MN 24; LOHR4 includes PMOS transistors MP 19-MP 24 and NMOS transistors MN 25-MN 32; Node N1 is connected to MP2, MP6, MP21, MN1 and MN 29; node N2 is connected to MP1, MN2, MN3, MN6 and MN 15; Node N3 is connected to MP5, MN3, MN5, MN6, MN8 and MN 12; Node N4 is connected to MP2, MP6, MP16, MN18 and MN 8; Node N5 is connected to MP3, MP