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CN-122026890-A - Interface circuit, chip and electronic equipment

CN122026890ACN 122026890 ACN122026890 ACN 122026890ACN-122026890-A

Abstract

The application provides an interface circuit, a chip and electronic equipment, relates to the field of interface circuits, and can improve an ESD design window through circuit design. The interface circuit comprises a control circuit, a front-stage driving circuit and a rear-stage driving circuit. The control circuit is connected with the front-stage driving circuit. The front-stage driving circuit comprises a first output end, a second output end, a third output end and a fourth output end. The rear-stage driving circuit comprises a second P-type transistor, a first N-type transistor and a second N-type transistor which are connected between a high-level power line and a low-level power line in a complementary symmetrical mode, and grid electrodes of the four transistors are respectively connected with a first output end, a second output end, a third output end and a fourth output end. The control circuit controls the second output end and the third output end of the front-stage driving circuit to hang under the control of high pulse voltage on the high-level power line, the first output end outputs high level, and the fourth output end outputs low level.

Inventors

  • WANG QIN

Assignees

  • 华为技术有限公司

Dates

Publication Date
20260512
Application Date
20241111

Claims (11)

  1. 1. An interface circuit is characterized by comprising a high-level power line, a low-level power line, a control circuit, a front-stage driving circuit and a rear-stage driving circuit, wherein the control circuit, the front-stage driving circuit and the rear-stage driving circuit are connected with the high-level power line and the low-level power line; the control circuit is connected with the front-stage driving circuit; The front-stage driving circuit comprises a first output end, a second output end, a third output end and a fourth output end; The rear-stage driving circuit comprises a first P-type transistor, a second P-type transistor, a first N-type transistor and a second N-type transistor, wherein the source electrode of the second P-type transistor is connected with the high-level power line, the drain electrode of the second P-type transistor is connected with the source electrode of the first P-type transistor, the grid electrode of the second P-type transistor is connected with the first output end, the drain electrode of the first P-type transistor is connected with a connecting disc of a chip, the grid electrode of the first P-type transistor is connected with the second output end, the source electrode of the second N-type transistor is connected with the low-level power line, the drain electrode of the second N-type transistor is connected with the source electrode of the first N-type transistor, the grid electrode of the second N-type transistor is connected with the fourth output end, the drain electrode of the first N-type transistor is connected with the connecting disc, and the grid electrode of the first N-type transistor is connected with the third output end; the control circuit controls the second output end and the third output end of the front-stage driving circuit to be suspended under the control of high pulse voltage on the high-level power line, the first output end outputs high level, and the fourth output end outputs low level.
  2. 2. The interface circuit of claim 1, wherein, The rear-stage driving circuit also comprises a first diode and a second diode; The positive electrode of the first diode is connected to the connecting disc, the negative electrode of the first diode is connected to the high-level power line, the positive electrode of the second diode is connected to the low-level power line, and the negative electrode of the first diode is connected to the connecting disc.
  3. 3. Interface circuit according to claim 1 or 2, characterized in that, The front-stage driving circuit further comprises a first input end; the control circuit outputs an input signal of the first input end to the connecting disc through the front-stage driving circuit and the rear-stage driving circuit under the control of the power supply voltage on the high-level power supply line.
  4. 4. An interface circuit according to any one of claims 1-3, characterized in that, The control circuit comprises a first resistor, a first capacitor, a third P-type transistor, a third N-type transistor, a first inverter, a second inverter, a first node, a first control end and a second control end; One end of the first resistor is connected with the high-level power line, and the other end of the first resistor is connected with the first node; One end of the first capacitor is connected with the first node, and the other end of the first capacitor is connected with the low-level power line; The grid electrode of the third P-type transistor and the grid electrode of the third N-type transistor are connected to the first node; the source electrode of the third P-type transistor is connected with the high-level power line, the source electrode of the third N-type transistor is connected with the low-level power line, and the drain electrode of the third P-type transistor and the drain electrode of the third N-type transistor are connected to the input end of the first inverter; The output end of the first inverter is connected with the input end of the second inverter, the output end of the first inverter is connected with the second control end, and the output end of the second inverter is connected with the first control end.
  5. 5. An interface circuit according to claim 3 or 4, characterized in that, The front-stage driving circuit comprises a first transmission gate, a second resistor and a third resistor; the control ends of the first transmission gate and the second transmission gate are connected with the second output end, and the opposite-phase control ends of the first transmission gate and the second transmission gate are connected with the first control end; one end of the second resistor is connected with the low-level power line, the second end of the second resistor is connected with the input end of the first transmission gate, and the output end of the first transmission gate is connected to the second output end; one end of the third resistor is connected with the high-level power line, the second end of the third resistor is connected with the input end of the second transmission gate, and the output end of the second transmission gate is connected to the third output end.
  6. 6. An interface circuit according to any one of claims 3-5, characterized in that, The front-stage driving circuit further comprises a third transmission gate, a fourth P-type transistor, a fourth N-type transistor, a third inverter and a fourth inverter; The control ends of the third transmission gate and the fourth transmission gate are connected with the second control end, and the opposite-phase control ends of the third transmission gate and the fourth transmission gate are connected with the first control end; The input end of the third inverter is connected with the first input end, the output end of the third inverter is connected with the input end of the third transmission gate, and the output end of the third transmission gate is connected with the first output end; the grid electrode of the fourth P-type transistor is connected with the second output end, the source electrode of the fourth P-type transistor is connected with the high-level power line, and the drain electrode of the fourth P-type transistor is connected with the first output end; The input end of the fourth inverter is connected with the first input end, the output end of the fourth inverter is connected with the input end of the fourth transmission gate, the output end of the fourth transmission gate is connected with the fourth output end, the grid electrode of the fourth N-type transistor is connected with the first control end, the source electrode of the fourth N-type transistor is connected with the low-level power line, and the drain electrode of the fourth N-type transistor is connected with the fourth output end.
  7. 7. Interface circuit according to any of the claims 4-6, characterized in that, The interface circuit further includes a fifth N-type transistor; The grid electrode of the fifth N-type transistor is connected with the input end of the first phase inverter, the source electrode of the fifth N-type transistor is connected with the low-level power line, and the drain electrode of the fifth N-type transistor is connected with the high-level power line.
  8. 8. A chip comprising a land and an interface circuit according to any one of claims 1-7, said interface circuit being connected to said land.
  9. 9. The chip of claim 8, wherein the first P-type transistor and the first N-type transistor are core devices.
  10. 10. The chip of claim 8, wherein all transistors in the interface circuit are core devices.
  11. 11. An electronic device comprising a chip as claimed in any one of claims 8-10 and a circuit board, said chip being electrically connected to said circuit board.

Description

Interface circuit, chip and electronic equipment Technical Field The present application relates to the field of interface circuits, and in particular, to an interface circuit, a chip, and an electronic device. Background In order to protect the chip from electrostatic discharge (electrostatic discharge, ESD), the chip design process is subject to strict constraints of ESD design rules, 1) the size of the ESD protection device, 2) the robustness of the ESD bleed path, and 3) the P2P (pointto point, point-to-point) resistance on the ESD bleed path. In addition, designers working on interface/ESD designs also need to ensure that the ESD protection device operates within a pre-designed ESD design window. Referring to fig. 1, the ESD design window specifies that the ESD protection device can operate within a range of voltages and currents that are normal when an ESD event occurs. It is commonly determined by the operating voltage (V DD), breakdown voltage (Vbd), turn-on voltage (Vt 1), snapback voltage (Vsp), secondary breakdown voltage (Vt 2) of the ESD protection device, etc. of the protected circuit. ESD protection devices need to be triggered on above normal circuit operating voltages, and also to be guaranteed to fail before the breakdown voltage of the protected device is reached. That is, we need to ensure Vsp > V DD, vt1< Vt2< Vbd, and leave sufficient margin (margin). However, as the process node is more advanced, the channel length and gate oxide thickness of the device are continuously reduced, and the breakdown voltage (Vbd) is continuously reduced, so that the ESD design window is narrower, the design margin is smaller, and the robustness is poorer. Disclosure of Invention The application provides an interface circuit, a chip and electronic equipment, which can improve an ESD design window of the chip through circuit design. The application provides an interface circuit which comprises a high-level power line, a low-level power line, a control circuit, a front-stage driving circuit and a rear-stage driving circuit, wherein the control circuit, the front-stage driving circuit and the rear-stage driving circuit are connected with the high-level power line and the low-level power line. Wherein, the control circuit is connected with the front-stage driving circuit. The front-stage driving circuit comprises a first output end, a second output end, a third output end and a fourth output end. The rear-stage driving circuit comprises a first P-type transistor, a second P-type transistor, a first N-type transistor and a second N-type transistor. The source electrode of the second P-type transistor is connected with the high-level power line, the drain electrode of the second P-type transistor is connected with the source electrode of the first P-type transistor, the grid electrode of the second P-type transistor is connected with the first output end, the drain electrode of the first P-type transistor is connected with the connecting disc of the chip, and the grid electrode of the first P-type transistor is connected with the second output end. The source electrode of the second N-type transistor is connected with the low-level power line, the drain electrode of the second N-type transistor is connected with the source electrode of the first N-type transistor, the grid electrode of the second N-type transistor is connected with the fourth output end, the drain electrode of the first N-type transistor is connected to the connecting disc, and the grid electrode of the first N-type transistor is connected with the third output end. The control circuit controls the second output end and the third output end of the front-stage driving circuit to hang under the control of high pulse voltage on the high-level power line, the first output end outputs high level, and the fourth output end outputs low level. When the novel interface circuit is adopted, when an ESD event occurs, under the control of the control circuit and the front-stage driving circuit, the rear-stage driving circuit is driven to enter an ESD protection mode, the grid electrodes of the first P-type transistor and the first N-type transistor are suspended, the second P-type transistor and the second N-type transistor are both cut off, and in this case, the connecting disc (PAD) can be coupled to an intermediate level value through the first P-type transistor and the first N-type transistor, so that the level born by the first P-type transistor and the first N-type transistor can be reduced to about half (namely half of the level born by the first P-type transistor and the first N-type transistor before the connecting disc is coupled). That is, by changing the circuit design, the relative breakdown voltage that the circuit can withstand is greatly improved, the voltage withstanding capability of the channel and Gate Oxide (GOX) of the device is improved, and then the ESD design window of the chip is improved. In some possible implementations, the post