CN-122026892-A - Pressure converter

CN122026892ACN 122026892 ACN122026892 ACN 122026892ACN-122026892-A

Abstract

The invention relates to a transformer, which comprises a cross coupling circuit, a differential pair circuit, a NOT gate and a pull element. The NOT gate receives an input signal and generates an inverted input signal. The cross-coupling circuit is connected to the first node and the second node, and receives the first supply voltage and the voltage of the second node as an output signal. The differential pair circuit is connected to the first node and the second node, and receives a ground voltage, an input signal and an inverted input signal. The pull-up element is connected to the second node, and receives the enable signal. When the enable signal is inactive, the output signal is maintained at a particular logic level. When the enable signal acts, the output signal follows the variation of the input signal.

Inventors

HUANG ZHIYANG
WANG WEIQIANG
GU WEIMING
Zhong Chengtou
HUANG ZHIHAO

Assignees

力旺电子股份有限公司

Dates

Publication Date: 20260512
Application Date: 20251103
Priority Date: 20241112

Claims (17)

1. A voltage converter for converting an input signal having a signal range from a first supply voltage to a ground voltage to an output signal having a signal range from a second supply voltage to the ground voltage, the second supply voltage being greater than the first supply voltage, the voltage converter comprising: A first P-type transistor having a source receiving the second supply voltage, a drain coupled to a first node, a gate coupled to a second node, and a voltage at the second node as the output signal; A second P-type transistor having a source receiving the second supply voltage, a drain coupled to the second node, and a gate coupled to the first node; a first N-type transistor, a source electrode of the first N-type transistor receives the grounding voltage, a drain electrode of the first N-type transistor is coupled to a third node, and a grid electrode of the first N-type transistor receives the input signal; a second N-type transistor having a source receiving the ground voltage, a drain coupled to a fourth node, a gate receiving an inverted input signal, the input signal being complementary to the inverted input signal; A third N-type transistor, a source electrode of the third N-type transistor is coupled to the third node, a drain electrode of the third N-type transistor is coupled to the first node, and a gate electrode of the third N-type transistor receives the input signal; A fourth N-type transistor having a source coupled to the fourth node, a drain coupled to the second node, a gate receiving the inverted input signal, and A pull element connected to the second node; wherein the pull element receives an enable signal; The pull-up device is turned on and the output signal is maintained at a specific logic level when at least one of the first supply voltage and the second supply voltage is not yet supplied and the enable signal is not activated, and the pull-up device is turned off and the output signal is changed along with the change of the input signal when the first supply voltage and the second supply voltage are both supplied and the enable signal is activated.
2. The transformer of claim 1, further comprising: A third P-type transistor having a source receiving the first supply voltage, a drain coupled to the third node, a gate receiving the input signal, and A source of the fourth P-type transistor receives the first supply voltage, a drain of the fourth P-type transistor is coupled to the fourth node, and a gate of the fourth P-type transistor receives the inverted input signal.
3. The transformer of claim 2, wherein the first P-type transistor, the second P-type transistor, the third N-type transistor and the fourth N-type transistor are medium voltage devices, the third P-type transistor, the fourth P-type transistor, the first N-type transistor and the second N-type transistor are low-voltage elements.
4. The transformer of claim 3, wherein the first P-type transistor, the second P-type transistor, the third P-type transistor, the fourth P-type transistor, the first N-type transistor and the second N-type transistor are metal oxide semiconductor field effect transistors, the third N-type transistor and the fourth N-type transistor are depletion transistors.
5. The voltage transformer of claim 2 wherein the enable signal is the ground voltage when the enable signal is inactive, and the enable signal is the second supply voltage when the enable signal is active.
6. The voltage transformer according to claim 5, wherein the pull-up device comprises a fifth P-type transistor having a source receiving the second supply voltage, a drain connected to the second node, and a gate receiving the enable signal.
7. The transformer of claim 6, further comprising: a fifth N-type transistor having its source coupled to the third node via the fifth N-type transistor, and A sixth N-type transistor, the source of the fourth N-type transistor being coupled to the fourth node via the sixth N-type transistor; the drain electrode of the fifth N-type transistor is connected to the source electrode of the third N-type transistor, the source electrode of the fifth N-type transistor is connected to the third node, the grid electrode of the fifth N-type transistor receives the enabling signal, and the fifth N-type transistor is started when the enabling signal acts; The drain of the sixth N-type transistor is connected to the source of the fourth N-type transistor, the source of the sixth N-type transistor is connected to the fourth node, the gate of the sixth N-type transistor receives the enable signal, and the sixth N-type transistor is turned on when the enable signal acts.
8. The transformer of claim 6, further comprising: a fifth N-type transistor having its drain coupled to the first node via the fifth N-type transistor, and A sixth N-type transistor, the drain of the fourth N-type transistor being coupled to the second node via the sixth N-type transistor; The drain electrode of the fifth N-type transistor is connected to the first node, the source electrode of the fifth N-type transistor is connected to the drain electrode of the third N-type transistor, the grid electrode of the fifth N-type transistor receives the enabling signal, and the fifth N-type transistor is started when the enabling signal acts; The drain of the sixth N-type transistor is connected to the second node, the source of the sixth N-type transistor is connected to the drain of the fourth N-type transistor, the gate of the sixth N-type transistor receives the enable signal, and the sixth N-type transistor is turned on when the enable signal acts.
9. The transformer of claim 6, further comprising: A fifth N-type transistor having the drain coupled to the third node via the fifth N-type transistor, and A sixth N-type transistor, the drain of the fourth P-transistor being coupled to the fourth node via the sixth N-type transistor; The drain electrode of the fifth N-type transistor is connected to the drain electrode of the third P-type transistor, the source electrode of the fifth N-type transistor is connected to the third node, the grid electrode of the fifth N-type transistor receives the enabling signal, and the fifth N-type transistor is started when the enabling signal acts; the drain of the sixth N-type transistor is connected to the drain of the fourth P-type transistor, the source of the sixth N-type transistor is connected to the fourth node, the gate of the sixth N-type transistor receives the enable signal, and the sixth N-type transistor is turned on when the enable signal acts.
10. The voltage transformer according to claim 5, wherein the pull-up device comprises a fifth N-type transistor having a source receiving the ground voltage, a drain connected to the second node, and a gate receiving an inverted enable signal complementary to the inverted enable signal.
11. The voltage transformer of claim 10, further comprising a switching element, the source of the first P-type transistor receiving the second supply voltage via the switching element, and the source of the second P-type transistor receiving the second supply voltage via the switching element, and the switching element being turned on when the enable signal is asserted.
12. The voltage transformer of claim 11, wherein the switching element comprises a fifth P-type transistor, a source electrode of the fifth P-type transistor receives the second supply voltage, a drain electrode of the fifth P-type transistor is connected to the source electrode of the first P-type transistor, a drain electrode of the fifth P-type transistor is connected to the source electrode of the second P-type transistor, a gate electrode of the fifth P-type transistor receives the inverted enable signal, and the fifth P-type transistor is turned on when the enable signal acts.
13. The voltage transformer of claim 11 wherein the switching element comprises a fifth P-type transistor and a sixth P-type transistor, a source of the fifth P-type transistor receiving the second supply voltage, a drain of the fifth P-type transistor being connected to the source of the first P-type transistor and a gate of the fifth P-type transistor receiving the inverted enable signal and the fifth P-type transistor being turned on when the enable signal is active, and a source of the sixth P-type transistor receiving the second supply voltage, a drain of the sixth P-type transistor being connected to the source of the second P-type transistor and a gate of the sixth P-type transistor receiving the inverted enable signal and the sixth P-type transistor being turned on when the enable signal is active.
14. The transformer of claim 11, further comprising: a sixth N-type transistor having its source coupled to the third node via the sixth N-type transistor, and A seventh N-type transistor, the source of the fourth N-type transistor being coupled to the fourth node via the seventh N-type transistor; the drain electrode of the sixth N-type transistor is connected to the source electrode of the third N-type transistor, the source electrode of the sixth N-type transistor is connected to the third node, the grid electrode of the sixth N-type transistor receives the enabling signal, and the sixth N-type transistor is started when the enabling signal acts; the drain electrode of the seventh N-type transistor is connected to the source electrode of the fourth N-type transistor, the source electrode of the seventh N-type transistor is connected to the fourth node, the grid electrode of the seventh N-type transistor receives the enabling signal, and the seventh N-type transistor is started when the enabling signal acts.
15. The transformer of claim 11, further comprising: a sixth N-type transistor having its drain coupled to the first node via the sixth N-type transistor, and A seventh N-type transistor, the drain of the fourth N-type transistor being coupled to the second node via the seventh N-type transistor; The drain electrode of the sixth N-type transistor is connected to the first node, the source electrode of the sixth N-type transistor is connected to the drain electrode of the third N-type transistor, the grid electrode of the sixth N-type transistor receives the enabling signal, and the sixth N-type transistor is started when the enabling signal acts; the drain electrode of the seventh N-type transistor is connected to the second node, the source electrode of the seventh N-type transistor is connected to the drain electrode of the fourth N-type transistor, the grid electrode of the seventh N-type transistor receives the enabling signal, and the seventh N-type transistor is started when the enabling signal acts.
16. The transformer of claim 11, further comprising: A sixth N-type transistor, the drain of the third P-type transistor being coupled to the third node via the sixth N-type transistor, and A seventh N-type transistor, the drain of the fourth P-type transistor being coupled to the fourth node via the seventh N-type transistor; The drain electrode of the sixth N-type transistor is connected to the drain electrode of the third P-type transistor, the source electrode of the sixth N-type transistor is connected to the third node, the grid electrode of the sixth N-type transistor receives the enabling signal, and the sixth N-type transistor is started when the enabling signal acts; The drain of the seventh N-type transistor is connected to the drain of the fourth P-type transistor, the source of the seventh N-type transistor is connected to the fourth node, the gate of the seventh N-type transistor receives the enable signal, and the seventh N-type transistor is turned on when the enable signal acts.
17. The transformer of claim 10, further comprising: A fifth P-type transistor, the drain of the first P-type transistor being coupled to the first node via the fifth P-type transistor, and A sixth P-type transistor, the drain of the second P-type transistor being coupled to the second node via the sixth P-type transistor; the source electrode of the fifth P-type transistor is connected to the drain electrode of the first P-type transistor, the drain electrode of the fifth P-type transistor is connected to the first node, the grid electrode of the fifth P-type transistor receives the reverse phase enabling signal, and the fifth P-type transistor is started when the enabling signal acts; The source of the sixth P-type transistor is connected to the drain of the second P-type transistor, the drain of the sixth P-type transistor is connected to the second node, the gate of the sixth P-type transistor receives the inverted enable signal, and the sixth P-type transistor is turned on when the enable signal acts.

Description

Pressure converter Technical Field The present invention relates to an electrical circuit, and in particular to a voltage converter (LEVEL SHIFTER). Background Generally, there are different power domains (power domains) in an IC chip, and circuits in the different power domains receive different supply voltages (supply voltages). For example, the supply voltage of the V DD1 power domain is V DD1,VDD2 power domain is V DD2, and the supply voltage V DD1 is different from the supply voltage V DD2. For example, the supply voltage V DD1 is 1.2V and the supply voltage V DD2 is 5V. Furthermore, today's CMOS semiconductor processes may provide different processes for the voltage operating range of the device. For example, a transistor with high voltage stress (MV) may be manufactured by using a medium voltage device (medium voltage device) process, and the manufactured transistor is suitable for medium voltage operation (medium voltage operation). In addition, a transistor with a faster operation speed but lower voltage stress can be manufactured by using a low voltage device (low voltage device, LV device) process, and the manufactured transistor is suitable for low voltage operation (low voltage operation). For example, the voltage stress between the gate and the source of the transistor is about 3.0 v-10 v during medium voltage operation, and about 0.8 v-2.0 v during low voltage operation. Referring to fig. 1A, a schematic diagram of the circuit operation between different power domains in an IC chip is shown. In the V DD1 power domain of the IC chip 100, the signal of the first circuit 102 is a logic high level (logic HIGH LEVEL) of the supply voltage V DD1 and a logic low level (logic low level) of the ground voltage GND. In the V DD2 power domain of the IC chip 100, the signal of the second circuit 106 is the supply voltage V DD2 with the logic high level and the ground voltage GND with the logic low level. Furthermore, the signals between the different power domains need to be converted by the voltage converter (LEVEL SHIFTER) 104 to make the communication (communication) between the circuits in the different power domains normal. Basically, the main circuit (i.e., the second circuit 106) in the IC chip is designed in the V DD2 power domain, and only a small portion of the circuit (i.e., the first circuit 102) is designed in the V DD1 power domain. For example, the first circuit 102 communicates with the second circuit 106 using the control signal C TRL1. At this time, the transformer 104 receives the control signal C TRL1 of the first circuit 102 as the input signal IN of the transformer 104, and the output signal OUT generated by the transformer 104 is used as another control signal C TRLA and is transmitted to the second circuit 106. That is, the transformer 104 may transform the control signal C TRL1 of the logic high level (i.e., V DD1) in the V DD1 power domain into the control signal C TRLA of the logic high level (i.e., V DD2) in the V DD2 power domain. In addition, the transformer 104 can also transform the control signal C TRL1 with logic low level (i.e. GND) in the V DD1 power domain into the control signal C TRLA with logic low level (i.e. GND) in the V DD2 power domain. Thus, the two circuits 102, 106 can communicate normally. Of course, if the first circuit 102 uses more control signals to communicate with the second circuit 106, more voltage converters are required. For example, when the first circuit 102 communicates with the second circuit 106 using ten control signals, ten voltage converters are required to perform logic level conversion of the ten control signals. Referring to fig. 1B, a conventional transformer is shown. The transformer 110 transforms the input signal IN and the inverted input signal ZIN having a signal range from the supply voltage V DD1 to the ground voltage GND into the output signal OUT having a signal range from the supply voltage V DD2 to the ground voltage GND. The supply voltage V DD1 may be, for example, 1.2V, the supply voltage V DD2 may be, for example, 5V, and the ground voltage GND may be 0V. That is, the supply voltage V DD2 is greater than the supply voltage V DD1, and the supply voltage V DD1 is greater than the ground voltage GND. As shown in fig. 1B, the transformer 110 includes a NOT gate 116, a cross-coupled circuit 112, and a differential pair circuit (DIFFERENTIAL PAIR circuits) 114. The NOT gate 116 is designed in the V DD1 power domain, and the cross-coupling circuit 112 and the differential pair circuit 114 are designed in the V DD2 power domain. Furthermore, the cross-coupling circuit 112 includes a P-type transistor M P1 and a P-type transistor M P2. The differential pair circuit 114 includes an N-type transistor M N1 and an N-type transistor M N2. The P-type transistor M P1、MP2 and the N-type transistor M N1、MN2 are Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET transistors for short). The two power terminals (power terminal) of the