Search

CN-122026897-A - Inverter, inverter module and control method of inverter

CN122026897ACN 122026897 ACN122026897 ACN 122026897ACN-122026897-A

Abstract

An inverter, an inverter module and a control method of the inverter are provided, wherein the inverter comprises a first transistor and a second transistor, a grid electrode of the first transistor is connected to a first input end, a grid electrode of the second transistor is connected to a second input end, a first node is arranged between the first input end and the grid electrode of the first transistor, a second node is arranged between the second input end and the grid electrode of the second transistor, a bias temperature instability recovery unit is connected to the first node and the second node respectively and used for enabling a passage to be formed between the first node and the second node when the first transistor and the second transistor are in an operating state, enabling a break to be formed between the first node and the second node when the first transistor and the second transistor are in a recovery state, and providing a first recovery voltage signal for the first node and a second recovery voltage signal for the second node. The inverter is capable of recovering bias temperature instability of the inverter.

Inventors

  • YU ANQI

Assignees

  • 中芯国际集成电路制造(上海)有限公司

Dates

Publication Date
20260512
Application Date
20241112

Claims (11)

  1. 1. An inverter for an inverter of the type described, characterized by comprising the following steps: A first transistor and a second transistor having different conductivity types, the gate of the first transistor being connected to a first input terminal and the gate of the second transistor being connected to a second input terminal, wherein a first node is provided between the first input terminal and the gate of the first transistor, and a second node is provided between the second input terminal and the gate of the second transistor; And the bias temperature instability recovery unit is respectively connected to the first node and the second node and is used for enabling a passage to be formed between the first node and the second node when the first transistor and the second transistor are in an operating state, enabling a circuit to be broken between the first node and the second node when the first transistor and the second transistor are in a recovery state, and providing a first recovery voltage signal for the first node and a second recovery voltage signal for the second node.
  2. 2. The inverter of claim 1, wherein the bias temperature instability recovery unit includes a third transistor connected between a first node and a second node, and a first switching transistor connected to the first node and a second switching transistor connected to the second node; The third transistor is used for controlling on-off between a first node and a second node based on states of the first transistor and the second transistor, the first switch is used for providing a first recovery voltage signal for the first node when the first transistor and the second transistor are in a recovery state, and the second switch is used for providing a second recovery voltage signal for the second node when the first transistor and the second transistor are in a recovery state.
  3. 3. The inverter of claim 2, wherein the third transistor has a source connected to the first node, a drain connected to the second node, and a gate connected to the first control terminal; The first control terminal is used for providing a first control signal, wherein the first control signal is used for controlling the third transistor to be in an on state when the first transistor and the second transistor are in a working state, and controlling the third transistor to be in an off state when the first transistor and the second transistor are in a recovery state.
  4. 4. The inverter of claim 2, wherein the first switching tube has one end connected to a first node and the other end connected to a first recovery voltage terminal for providing a first recovery voltage signal, and wherein the second switching tube has one end connected to a second node and the other end connected to a second recovery voltage terminal for providing a second recovery voltage signal; When the first transistor and the second transistor are in a recovery state, the first switch tube is conducted so as to provide a first recovery voltage signal for the first transistor; And when the first transistor and the second transistor are in a recovery state, the second switch transistor is conducted so as to provide a second recovery voltage signal for the second transistor.
  5. 5. The inverter of claim 4, wherein the first switching tube is a first diode and the second switching tube is a second diode; The first recovery voltage end provides a first recovery voltage signal when the first transistor and the second transistor are in a recovery state, and provides a first closing signal when the first transistor and the second transistor are in a working state, wherein the first closing signal is used for closing the first diode; The first transistor is an NMOS transistor, the positive electrode of the second diode is connected to the second node, the negative electrode of the second diode is connected to a second recovery voltage end, the second recovery voltage end provides a second recovery voltage signal when the first transistor and the second transistor are in a recovery state, and the second recovery voltage end provides a second closing signal when the first transistor and the second transistor are in a working state, and the second closing signal is used for closing the second diode.
  6. 6. The inverter of claim 2, wherein the bias temperature instability recovery unit further comprises a fourth transistor connected to a third node and a fourth node, the third node being a node between the first input terminal and the gate of the first transistor, the fourth node being a node between the second input terminal and the gate of the second transistor, the fourth transistor being configured to control on-off between the third node and the fourth node based on states of the first transistor and the second transistor.
  7. 7. The inverter of claim 6, wherein the fourth transistor has a source connected to the third node, a drain connected to the fourth node, and a gate connected to the second control terminal; The second control terminal is configured to provide a second control signal, where the second control signal is configured to control the fourth transistor to be in an on state when the first transistor and the second transistor are in a working state, and control the fourth transistor to be in an off state when the first transistor and the second transistor are in a recovery state.
  8. 8. The inverter of claim 6, wherein the well in which the third transistor is located is isolated from the wells in which the first and second transistors are located, and wherein the well in which the fourth transistor is located is isolated from the wells in which the first and second transistors are located.
  9. 9. The inverter of claim 1, wherein the first transistor is a PMOS transistor, the first recovery voltage signal being for causing the first transistor to undergo a negative bias temperature instability recovery; The second transistor is an NMOS transistor, and the second recovery voltage signal is used for enabling the second transistor to recover the forward bias temperature instability; The source electrode of the first transistor is connected to a first voltage source, the drain electrode of the first transistor is connected to a first output end, the source electrode of the second transistor is connected to a second voltage source, and the drain electrode of the second transistor is connected to a second output end.
  10. 10. A control method of an inverter, wherein the inverter includes a first transistor and a second transistor having different conductivity types, a gate of the first transistor is connected to a first input terminal, a gate of the second transistor is connected to a second input terminal, wherein a first node is provided between the first input terminal and the gate of the first transistor, and a second node is provided between the second input terminal and the gate of the second transistor, the method comprising: when the first transistor and the second transistor are in a working state, a passage is controlled between the first node and the second node; And when the first transistor and the second transistor are in a recovery state, controlling the first node and the second node to be disconnected, providing a first recovery voltage signal for the first node, and providing a second recovery voltage signal for the second node.
  11. 11. An inverter module comprising a plurality of inverters according to any one of claims 1 to 9 connected in sequence; the first output end of the front inverter is connected to the second input end of the back inverter in the direction of the signal transmission path, and the second output end of the front inverter is connected to the first input end of the back inverter.

Description

Inverter, inverter module and control method of inverter Technical Field The embodiment of the disclosure relates to the field of integrated circuits, in particular to an inverter, an inverter module and a control method of the inverter. Background Bias temperature instability (Bias Temperature Instability, BTI) refers to degradation effects such as threshold voltage drift, saturation current reduction, etc. of the electrical characteristics of a transistor when bias voltage is applied to the gate of the transistor under certain temperature conditions. Bias temperature instability includes reverse bias temperature instability (Negative Bias Temperature Instability, NBTI) that occurs with PMOS transistors and forward bias temperature instability (Positive Bias Temperature Instability, PBTI) that occurs with NMOS transistors. Bias temperature instability recovery is achieved by applying a preset bias voltage to the transistor such that the performance of the transistor is recovered to some extent. However, the inverter is a device that allows the gates of the PMOS transistor and the NMOS transistor to be shared, and the corresponding bias temperature instability recovery is to be improved. Disclosure of Invention The embodiment of the disclosure is used for providing an inverter, an inverter module and a control method of the inverter, which can improve the recovery of the bias temperature instability of the inverter and improve the electrical performance of the inverter. To solve the above-described problems, an embodiment of the present disclosure provides an inverter including: A first transistor and a second transistor having different conductivity types, the gate of the first transistor being connected to a first input terminal and the gate of the second transistor being connected to a second input terminal, wherein a first node is provided between the first input terminal and the gate of the first transistor, and a second node is provided between the second input terminal and the gate of the second transistor; And the bias temperature instability recovery unit is respectively connected to the first node and the second node and is used for enabling a passage to be formed between the first node and the second node when the first transistor and the second transistor are in an operating state, enabling a circuit to be broken between the first node and the second node when the first transistor and the second transistor are in a recovery state, and providing a first recovery voltage signal for the first node and a second recovery voltage signal for the second node. Optionally, the bias temperature instability recovery unit includes a third transistor connected between the first node and the second node, and a first switching transistor connected to the first node and a second switching transistor connected to the second node; The third transistor is used for controlling on-off between a first node and a second node based on states of the first transistor and the second transistor, the first switch is used for providing a first recovery voltage signal for the first node when the first transistor and the second transistor are in a recovery state, and the second switch is used for providing a second recovery voltage signal for the second node when the first transistor and the second transistor are in a recovery state. Optionally, the source electrode of the third transistor is connected to the first node, the drain electrode is connected to the second node, and the gate electrode is connected to the first control end; The first control terminal is used for providing a first control signal, wherein the first control signal is used for controlling the third transistor to be in an on state when the first transistor and the second transistor are in a working state, and controlling the third transistor to be in an off state when the first transistor and the second transistor are in a recovery state. Optionally, one end of the first switch tube is connected to a first node, the other end is connected to a first recovery voltage end, and the first recovery voltage end is used for providing a first recovery voltage signal; When the first transistor and the second transistor are in a recovery state, the first switch tube is conducted so as to provide a first recovery voltage signal for the first transistor; And when the first transistor and the second transistor are in a recovery state, the second switch transistor is conducted so as to provide a second recovery voltage signal for the second transistor. Optionally, the first switching tube is a first diode, and the second switching tube is a second diode; The first recovery voltage end provides a first recovery voltage signal when the first transistor and the second transistor are in a recovery state, and provides a first closing signal when the first transistor and the second transistor are in a working state, wherein the first closing signal is used for closing the fir