CN-122026899-A - Frequency division circuit, chip and control method of signal frequency division

CN122026899ACN 122026899 ACN122026899 ACN 122026899ACN-122026899-A

Abstract

The embodiment of the application provides a frequency dividing circuit, a chip and a control method for signal frequency division, which comprise n first control units, second control units and third control units, wherein n is an integer greater than or equal to 0, the input ends of the first control units and the second control units are respectively connected with control signals output by a control module, the output end of the first control unit is connected with the input end of the second control unit, the output end of the second control unit is connected with the input end of the third control unit, the input ends of the first control unit, the second control unit and the third control unit are also connected with the input signals, the third control unit is used for outputting frequency dividing signals corresponding to the input signals, the frequency dividing signals can be adapted to signals with different frequency dividing ratios, the configurable range of the frequency dividing ratio is large and continuous, and the area and the power consumption of the frequency divider are reduced.

Inventors

WANG SHENGZHUO
WANG XIN
ZHANG ZHENWEI

Assignees

昆腾微电子股份有限公司

Dates

Publication Date: 20260512
Application Date: 20260126

Claims (12)

1. The frequency dividing circuit is characterized by comprising n first control units, a second control unit and a third control unit, wherein n is an integer larger than or equal to 0, the input ends of the first control units and the second control units are respectively connected with control signals output by a control module, the output end of the first control unit is connected with the input end of the second control unit, the output end of the second control unit is connected with the input end of the third control unit, the input ends of the first control unit, the second control unit and the third control unit are further connected with input signals, and the third control unit is used for outputting frequency dividing signals corresponding to the input signals, wherein the frequency dividing signals are determined according to target control signals output by the control module, and the target control signals comprise one or more of frequency dividing ratio, duty ratio and phase of the frequency dividing signals.
2. The frequency divider circuit of claim 1, wherein the control module is configured to output a first control signal and a second control signal, the first control signal being coupled to the inputs of the first control signal and the second control signal, respectively, the second control signal being further coupled to the input of the first control unit, the first control signal being configured to provide delay times for the first control unit and the second control unit, respectively, and the second control signal being configured to provide a transition of the output signals.
3. The frequency divider circuit of claim 2, wherein the first control unit includes n first flip-flops, a second flip-flop, a third flip-flop, a first inverter, and a first selector, wherein input terminals of the n first flip-flops are connected to the first control signal, output terminals of the first flip-flops are connected to an enable terminal of the first selector, output terminals of the second flip-flops are connected to an input terminal of the third flip-flop, output terminals of the third flip-flops are connected to an input terminal of the first inverter, and output terminals of the first inverter and the second flip-flop are respectively connected to input terminals of the first selector.
4. The frequency divider circuit of claim 3, wherein the second control unit comprises n+1 fourth flip-flops, a fifth flip-flop, a sixth flip-flop, a second inverter, and a second selector, wherein an input terminal of the n+1 fourth flip-flops is connected to the second control signal, and an output terminal of the fourth flip-flop is connected to an enable terminal of the second selector; The input end of the fifth trigger is connected with the output end of the first selector of the first control unit, the output end of the fifth trigger is connected with the input end of the sixth trigger, the output end of the sixth trigger is connected with the input end of the second reverser, and the output end of the second reverser and the output end of the fifth trigger are respectively connected with the input end of the second selector.
5. The frequency divider circuit of claim 4, wherein control signals of the first selector and the second selector are opposite.
6. The frequency divider circuit of claim 5, wherein an output of the second inverter is coupled to an input of the third control unit.
7. A chip comprising a frequency dividing circuit as claimed in any one of claims 1 to 6.
8. The chip of claim 7, further comprising a synchronization module, an input signal generation module, a clock mask module, a control module, and the frequency division circuit, wherein: the synchronization module and the clock shielding module are used for performing synchronization or resetting processing on the input signals generated by the input signal generating module; the input signal generating module is used for generating a basic input signal according to the PLL clock signal: the control module is used for setting the frequency division ratio, the duty ratio and the phase of the frequency division signal of the control signal respectively to generate the target control signal.
9. The chip of claim 8, wherein the control module comprises a control pin, a configuration pin, a parameter pin and an output pin, wherein each of the output pins is connected to one of the frequency dividing circuits.
10. A control method for signal frequency division, characterized in that it is applied to a frequency division circuit according to any one of claims 1 to 6 or a chip according to any one of claims 7 to 9, said method comprising: Acquiring an input signal; and carrying out frequency division processing on the input signal according to a preset target control signal to obtain a frequency division signal corresponding to the input signal, wherein the target control signal at least comprises one or more of frequency division ratio, duty ratio and phase of the frequency division signal.
11. The method of claim 10, wherein prior to the acquiring the input signal, the method further comprises: selecting configuration pins in the control module; and based on the configuration pins, respectively carrying out parameter configuration on one or more corresponding parameter pins to obtain target parameters, wherein the parameter pins at least comprise high level quantity, low level quantity and phase delay information.
12. The method according to claim 10, wherein the step of performing frequency division processing on the input signal according to a preset target control signal to obtain a frequency-divided signal corresponding to the input signal includes: selecting a control pin in the control module; acquiring target parameters corresponding to the control pins based on the control pins; Controlling the corresponding output pins to output target control signals according to the target parameters; And according to the target control signal, carrying out frequency division processing on the input signal to obtain a frequency division signal corresponding to the input signal.

Description

Frequency division circuit, chip and control method of signal frequency division Technical Field The application relates to the technical field of chips, in particular to a frequency dividing circuit, a chip and a control method for signal frequency division. Background Currently, in radio FM/AM broadcasting, a wideband radio frequency receiver gradually replaces a conventional narrowband receiver, which is capable of simultaneously receiving and digitizing all channels of the entire frequency band, and multi-channel reception is achieved by a single radio frequency receiver and one PLL. Since the selection of the channel is done in the digital domain, it requires only a PLL of fixed frequency and a simple frequency division scheme to obtain the local oscillator signal of the mixer, the sampling clock of the ADC and the corresponding digital clock. The problem of VCO pulling and spurious interference is an important bottleneck for automotive electronic multi-band and multi-channel radio receivers. Therefore, the PLL frequency needs to be referred to a very high frequency band for frequency division, which is a great challenge for the area, power consumption and supportable frequency division ratio range of the frequency divider, and the corresponding quadrature 4 phase and differential overlap clock signals need to be provided by the PLL for the receiver and ADC, which requires that the frequency divider have strict reliability requirements for the relative phase relationship and duty cycle of the divided signals to meet the specification of the vehicle-level chip. Currently, a multi-mode frequency dividing unit is adopted to realize fixed frequency dividing ratio, but only a limited frequency dividing ratio range is supported in the mode, and if a larger frequency dividing ratio is needed, the multi-mode frequency dividing unit needs to be added, so that power consumption and area are increased sharply. Disclosure of Invention According to the technical scheme, the distribution circuit comprises n first control units, second control units and third control units, n is an integer larger than or equal to 0, the input ends of the first control units and the second control units are respectively connected with control signals output by the control modules, the output ends of the first control units are connected with the input ends of the second control units, the output ends of the second control units are connected with the input ends of the third control units, the input ends of the first control units, the second control units and the third control units are also connected with input signals, and the third control units are used for outputting frequency division signals corresponding to the input signals, wherein the frequency division signals are determined according to target control signals output by the control modules, the target control signals comprise one or more of frequency division ratios, duty ratios and phases of the frequency division signals, the output ends of the first control units are connected with the input ends of the third control units, the first control units, the second control units and the input ends of the third control units are connected with the input signals, the frequency division signals are set according to the target frequency division signals, the frequency division signals can be continuously matched with the frequency division signals, the frequency division signals can be generated according to the target frequency division signals, the frequency division signals are different in the target power consumption ratio, the frequency division ratio can be controlled by the control signals, the frequency division signals can be continuously, the frequency division signals can be matched with the target frequency division signals, and the frequency division signals can be controlled by the target frequency division signals, and the frequency division signals can be continuously, and the frequency division signals can be controlled according to the target power consumption, and the frequency division signals can be different. In a first aspect, some embodiments of the present application provide a frequency dividing circuit, including n first control units, second control units, and third control units, where n is an integer greater than or equal to 0, input ends of the first control units and the second control units are respectively connected to control signals output by a control module, output ends of the first control units are connected to input ends of the second control units, output ends of the second control units are connected to input ends of the third control units, input ends of the first control units, the second control units, and the third control units are further connected to input signals, and the third control units are configured to output frequency dividing signals corresponding to the input signals, where the frequency dividing signals are determined