CN-122026900-A - Self-resonant frequency adjustable static frequency divider and clock circuit

CN122026900ACN 122026900 ACN122026900 ACN 122026900ACN-122026900-A

Abstract

The application provides a self-resonant frequency adjustable static frequency divider and a clock circuit, and relates to the technical field of circuits, wherein the frequency divider comprises a master latch and a slave latch; each latch in the master latch and the slave latch comprises a current source, an adjustable resistor unit, a differential amplification pair, a cross-coupling pair and a load resistor pair, wherein the current source is connected with a first current branch and a second current branch, the first current branch is connected with the load resistor pair through the differential amplification pair, the second current branch is connected with the load resistor pair through the cross-coupling pair, a first switching tube is arranged on the first current branch, and a second switching tube and the adjustable resistor unit which are connected in series are arranged on the second current branch. Therefore, an adjustable resistance unit is configured on the second current branch, the correlation between the resistance value of the adjustable resistance unit and the frequency of the frequency divider is established, a hardware basis is provided for frequency adjustment, and the self-resonance frequency of the frequency divider is adjusted by adjusting the resistance value of the adjustable resistance unit, so that the frequency requirements of different scenes are met.

Inventors

SU YONGBO
ZHANG SHUXING
LI YAOHUA
ZHANG YONGXIN
FENG KE
LV MINGYANG

Assignees

中国科学院微电子研究所

Dates

Publication Date: 20260512
Application Date: 20260203

Claims (10)

1. A self-resonant frequency adjustable static frequency divider, comprising a master latch and a slave latch; Each of the master latch and the slave latch includes a current source, an adjustable resistance unit, a differential amplification pair, a cross-coupled pair, and a load resistance pair; The current source is connected with a first current branch and a second current branch, wherein the first current branch is connected with the load resistor pair through the differential amplification pair, the second current branch is connected with the load resistor pair through the cross coupling pair, a first switching tube is arranged on the first current branch, and a second switching tube and an adjustable resistor unit which are connected in series are arranged on the second current branch.
2. The frequency divider of claim 1, wherein the adjustable resistance unit comprises a series resistance circuit and a resistance adjustment circuit, the series resistance circuit comprising N sequentially series-connected resistance elements; And the resistance value regulating circuit is used for conducting M resistors in the series resistor circuit to be connected into the second current branch, and M is smaller than or equal to N.
3. The frequency divider according to claim 2, characterized in that, The resistance value adjusting circuit comprises a first switch branch and N second switch branches; the first end of the first switch branch is connected with the head end of a first resistor in the series resistor circuit, and the second end of the first switch branch is connected with the output end of the adjustable resistor unit; The first end of each second switching branch is correspondingly connected with a node, the node is the tail end of a resistance element in the series resistance circuit, and the second end of each second switching branch is connected with the output end of the adjustable resistance unit.
4. The frequency divider according to claim 3, wherein, And switching tubes are arranged on the first switching branch and each second switching branch, and only one switching branch is allowed to be conducted at a time in the first switching branch and the N second switching branches.
5. The frequency divider according to any one of claims 1-4, characterized in that, The larger the resistance value of the adjustable resistance unit is, the higher the self-resonant frequency of the frequency divider is, the smaller the resistance value of the adjustable resistance unit is, and the lower the self-resonant frequency of the frequency divider is.
6. The frequency divider of claim 3, further comprising an input buffer; The clock input end of the master latch and the clock input end of the slave latch are both connected with the output end of the input buffer, the differential output end of the master latch is connected to the differential input end of the slave latch, the differential output end of the slave latch is connected with the differential input end of the master latch, and the input buffer is used for receiving the amplified differential clock, driving the master latch in the forward direction and driving the slave latch in the reverse direction.
7. The frequency divider of claim 6, further comprising an output buffer; The differential output end of the main latch is connected with the input end of the output buffer; or, the differential output end of the slave latch is connected with the input end of the output buffer; the output buffer is used for amplifying the output signal of the differential output end of the connected latch and then taking the amplified output signal as the output signal of the frequency divider.
8. The frequency divider of claim 1, wherein the pair of clock switching transistors in the latch comprises a first switching transistor Q1 and a second switching transistor Q2, the differential amplification pair comprises a transistor Q3 and a transistor Q4, and the cross-coupled pair comprises a transistor Q5 and a transistor Q6; An emitter of the transistor Q3, an emitter of the transistor Q4 and a collector of the first switching tube Q1 are connected to a node one, an emitter of the transistor Q5, an emitter of the transistor Q6 and a collector of the second switching tube Q2 are connected to a node two, an emitter of the second switching tube Q2 is connected to a second end of the adjustable resistor unit, and a first end of the adjustable resistor unit is connected to the current source; The collector of the transistor Q3, the collector of the transistor Q5 and the second end of the first resistor of the pair of load resistors are connected to node three, the collector of the transistor Q4, the collector of the transistor Q6 and the second end of the second resistor of the pair of load resistors are connected to node four, and the bases of both the transistor Q5 and the transistor Q6 are connected to each other's collectors.
9. A clock circuit comprising a self-resonant frequency-adjustable static frequency divider as claimed in any one of claims 1 to 8.
10. The clock circuit of claim 9, further comprising a controller; The controller is connected with the switching tubes included in the adjustable resistor unit and is used for controlling the on-off state of each switching tube included in the adjustable resistor unit and adjusting the resistance value of the adjustable resistor unit, wherein the larger the resistance value of the adjustable resistor unit is, the higher the self-resonant frequency of the frequency divider is.

Description

Self-resonant frequency adjustable static frequency divider and clock circuit Technical Field The present application relates to the field of circuit technologies, and in particular, to a self-resonant frequency adjustable static frequency divider and a clock circuit. Background Clock circuits (e.g., phase locked loop circuits, four-phase clock generation circuits) often require the use of frequency dividers to reduce the frequency of the signal to one-nth of the original frequency. The self-resonant frequency of the static frequency divider is that when no external small signal is input and a clock switch tube is in a conducting short circuit state, the internal equivalent ring oscillation of a circuit spontaneously generates a natural frequency of stable oscillation, but the frequency divider can increase the charge and discharge time of an output stage of the frequency divider and increase the signal transmission delay due to the reason that a capacitor, a resistor and the like are introduced by connecting a load, and further, the highest working frequency is reduced, so that the frequency divider is difficult to adapt to frequency requirements under different load conditions. Disclosure of Invention In view of the above, the present application provides a static frequency divider with adjustable self-resonant frequency and a clock circuit, which aims to realize the self-resonant frequency adjustment of the frequency divider. In a first aspect, the present application provides a self-resonant frequency adjustable static frequency divider and a clock circuit, comprising a master latch and a slave latch; Each of the master latch and the slave latch includes a current source, an adjustable resistance unit, a differential amplification pair, a cross-coupled pair, and a load resistance pair; The current source is connected with a first current branch and a second current branch, wherein the first current branch is connected with the load resistor pair through the differential amplification pair, the second current branch is connected with the load resistor pair through the cross coupling pair, a first switching tube is arranged on the first current branch, and a second switching tube and an adjustable resistor unit which are connected in series are arranged on the second current branch. Optionally, the adjustable resistance unit comprises a series resistance circuit and a resistance value adjusting circuit, and the series resistance circuit comprises N resistance elements which are sequentially connected in series; And the resistance value regulating circuit is used for conducting M resistors in the series resistor circuit to be connected into the second current branch, and M is smaller than or equal to N. Optionally, the resistance value adjusting circuit includes a first switching branch and N second switching branches; the first end of the first switch branch is connected with the head end of a first resistor in the series resistor circuit, and the second end of the first switch branch is connected with the output end of the adjustable resistor unit; The first end of each second switching branch is correspondingly connected with a node, the node is the tail end of a resistance element in the series resistance circuit, and the second end of each second switching branch is connected with the output end of the adjustable resistance unit. Optionally, the first switch branch and each second switch branch are provided with switch tubes, and only one switch branch is allowed to be turned on at a time in the first switch branch and the N second switch branches. Optionally, the larger the resistance value of the adjustable resistance unit is, the higher the self-resonant frequency of the frequency divider is, the smaller the resistance value of the adjustable resistance unit is, and the lower the self-resonant frequency of the frequency divider is. Optionally, the frequency divider further comprises an input buffer; The input end of the master latch clock and the clock input end of the slave latch are both connected with the output end of the input buffer, and the differential output end of the master latch is connected to the differential input end of the slave latch; the differential output end of the slave latch is connected with the differential input end of the master latch, and the input buffer is used for receiving the amplified differential clock, driving the master latch forward and driving the slave latch in opposite phase. Optionally, the frequency divider further comprises an output buffer; The differential output end of the main latch is connected with the input end of the output buffer; or, the differential output end of the slave latch is connected with the input end of the output buffer; the output buffer is used for amplifying the output signal of the differential output end of the connected latch and then taking the amplified output signal as the output signal of the frequency divider. Optionally,