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CN-122026903-A - Digital clock generating circuit capable of realizing rapid frequency calibration

CN122026903ACN 122026903 ACN122026903 ACN 122026903ACN-122026903-A

Abstract

The invention relates to a digital clock generation circuit capable of realizing rapid frequency calibration, which comprises a digital RC oscillator, a frequency divider, a counting sampling module, a frequency calibration module and a frequency calibration module, wherein the digital RC oscillator is provided with a control bus input end and a clock signal output end and is used for generating a digital clock signal CKOSC according to an input control value RFT, the frequency divider is provided with a control bus, a clock signal input end and a clock signal output end and is used for dividing frequency CKOSC according to an input control value NFT to generate a final digital clock output signal CKO, the counting sampling module is provided with a first clock signal input end, a second clock signal input end, a data bus and a trigger signal output end and is used for counting edges of the CKO under the driving of a reference clock signal CKP and outputting a count value SMP and a trigger digital signal CKSMP, and the frequency calibration module is provided with a clock signal, a trigger signal, a data bus input end and at least two control bus output ends and is used for calculating adjustment amounts of the RFT and the NFT according to the SMP and a preset target count value CN and adjusting RFT and according to CKSMP triggering.

Inventors

  • YIN YADONG
  • DAI LE
  • QUAN KAI
  • WU YUFAN

Assignees

  • 福州大学

Dates

Publication Date
20260512
Application Date
20260131

Claims (10)

  1. 1. A digital clock generation circuit capable of achieving fast frequency calibration, comprising: A digital RC oscillator having a control bus input and a clock signal output for generating a digital clock signal CKOSC based on an input control value RFT; A frequency divider having a control bus input, a clock signal input, and a clock signal output for dividing the digital clock signal CKOSC according to an input control value NFT to produce a final digital clock output signal CKO; The counting and sampling module is provided with a first clock signal input end, a second clock signal input end, a data bus output end and a trigger signal output end, and is used for counting the edges of the digital clock signal CKO under the drive of a reference clock signal CKP and outputting a count value SMP and a trigger digital signal CKSMP; The frequency calibration module is provided with a clock signal input end, a trigger signal input end, a data bus input end and at least two control bus output ends, and is used for calculating and obtaining adjustment amounts of control values RFT and NFT according to the count value SMP and a preset target count value CN, and carrying out iterative adjustment on the control values RFT and NFT according to a preset work flow and triggering the trigger digital signal CKSMP so as to calibrate the frequency of a final digital clock output signal CKO.
  2. 2. The rapid frequency calibration circuit of claim 1, wherein the counter sampling module operates in the following manner: after the counting operation is activated, when the first edge of the reference clock signal CKP arrives, the trigger digital signal CKSMP is set to the first level, and counting of the edges of the digital clock signal CKO is started; Stopping counting when the second edge of the reference clock signal CKP comes, setting the trigger digital signal CKSMP to a second level, and outputting the current count value as the count value SMP; the count value is then cleared and waits for the next count operation to activate.
  3. 3. The digital clock generation circuit of claim 2, wherein the count sampling module counts rising edges of the digital clock signal CKO.
  4. 4. The digital clock generation circuit of claim 1, wherein the workflow of the frequency calibration module comprises the steps of: Step S1, calculating a difference value between the count value SMP and a preset value CN to obtain a signed difference value wSMP; Step S2, calculating to obtain a corresponding adjustment quantity delta NFT according to the absolute value of the difference wSMP and the current control value NFT; Step S3, according to the sign of the difference wSMP, updating the control value NFT by using the adjustment quantity delta NFT; Step S4, calculating corresponding adjustment quantity delta RFT according to the absolute value of the difference wSMP and the current control value RFT; and S5, updating the control value RFT by using the adjustment quantity delta RFT according to the sign of the difference wSMP.
  5. 5. The digital clock generating circuit capable of realizing rapid frequency calibration according to claim 4, wherein in step S2, the adjustment amount Δnft is calculated by multiplying the current NFT value by the absolute value of the difference wSMP and dividing by the count value SMP to obtain Δnft; in step S4, the calculation method of the adjustment amount DeltaRFT is that the current RFT value is multiplied by the absolute value of the difference wSMP and divided by the preset value CN to obtain DeltaRFT.
  6. 6. The digital clock generation circuit of claim 4, wherein the frequency calibration module has a first mode of operation in which: 1) Firstly, executing step S1 and step S2; 2) Judging whether the delta NFT obtained in the step S2 is larger than or equal to 1: if yes, executing the step S3 to update the NFT value, executing the step S1 to recalculate wSMP after the step S3 is executed, and then executing the step S4 and the step S5 to adjust the RFT; If not, step S3 is skipped, and step S4 and step S5 are directly executed to adjust the RFT.
  7. 7. The digital clock generation circuit of claim 4, wherein the frequency calibration module has a second mode of operation in which: 1) Firstly, executing step S1 and step S4; 2) Judging whether DeltaRFT obtained in the step S4 is larger than or equal to 1: If yes, executing a step S5 to update the RFT value, executing a step S1 to recalculate wSMP after the step S5 is executed, and then executing a step S2 and a step S3 to adjust the NFT; If not, step S5 is skipped, and step S2 and step S3 are directly executed to adjust the NFT.
  8. 8. The digital clock generating circuit for implementing fast frequency calibration according to claim 1, wherein said frequency calibration module exits from an idle state and starts to execute a frequency calibration procedure when a rising edge of said trigger digital signal CKSMP arrives, and returns to the idle state after the procedure is completed.
  9. 9. The digital clock generating circuit according to claim 1, wherein the frequency calibration module further comprises an operation mode selection terminal MOD for receiving the external configuration signal to select different operation modes.
  10. 10. The digital clock generation circuit of claim 1, wherein the reference clock signal CKP has a frequency accuracy that is higher than an output clock frequency CKOSC of the digital RC oscillator when not divided.

Description

Digital clock generating circuit capable of realizing rapid frequency calibration Technical Field The invention relates to the technical field of integrated circuits, in particular to a digital clock generating circuit capable of realizing rapid frequency calibration. Background The RC oscillator is a widely applied clock generator due to its simple structure and flexible use. The oscillation frequency is inversely proportional to the time constant formed by the resistor (R) and the capacitor (C) in the circuit, and the output clock frequency can be changed by adjusting the RC time constant. However, the RC time constant is susceptible to external factors such as process deviation, power supply voltage fluctuation, and temperature variation, resulting in lower accuracy and poor stability of the output clock frequency. To ensure that the output clock has high frequency accuracy, the prior art generally adopts a frequency locking circuit such as a Phase Locked Loop (PLL) or a Frequency Locked Loop (FLL) to calibrate the output frequency of the RC oscillator in real time. Although the method can finally realize frequency locking, the locking process usually needs longer establishing time and has low convergence speed, and cannot meet certain application scenes with strict requirements on quick clock starting or quick calibration, such as wake-up clocks of low-power-consumption internet of things equipment, system chips needing frequent switching of working modes and the like. Therefore, how to significantly shorten the frequency calibration time of the RC oscillator without sacrificing the accuracy is a technical problem to be solved in the art. Disclosure of Invention The invention aims to overcome the defects of the prior art and provide a digital clock generating circuit capable of realizing rapid frequency calibration, which can finish accurate calibration of the output frequency of a digital RC oscillator in extremely short time, obviously improve the calibration speed and improve the starting performance and the response capability of a system. In order to achieve the purpose, the invention adopts the following technical scheme that the digital clock generating circuit capable of realizing rapid frequency calibration comprises: A digital RC oscillator having a control bus input and a clock signal output for generating a digital clock signal CKOSC based on an input control value RFT; A frequency divider having a control bus input, a clock signal input, and a clock signal output for dividing the digital clock signal CKOSC according to an input control value NFT to produce a final digital clock output signal CKO; The counting and sampling module is provided with a first clock signal input end, a second clock signal input end, a data bus output end and a trigger signal output end, and is used for counting the edges of the digital clock signal CKO under the drive of a reference clock signal CKP and outputting a count value SMP and a trigger digital signal CKSMP; The frequency calibration module is provided with a clock signal input end, a trigger signal input end, a data bus input end and at least two control bus output ends, and is used for calculating and obtaining adjustment amounts of control values RFT and NFT according to the count value SMP and a preset target count value CN, and carrying out iterative adjustment on the control values RFT and NFT according to a preset work flow and triggering the trigger digital signal CKSMP so as to calibrate the frequency of a final digital clock output signal CKO. Further, the working mode of the counting and sampling module is as follows: after the counting operation is activated, when the first edge of the reference clock signal CKP arrives, the trigger digital signal CKSMP is set to the first level, and counting of the edges of the digital clock signal CKO is started; Stopping counting when the second edge of the reference clock signal CKP comes, setting the trigger digital signal CKSMP to a second level, and outputting the current count value as the count value SMP; the count value is then cleared and waits for the next count operation to activate. Further, the count sampling module counts rising edges of the digital clock signal CKO. Further, the workflow of the frequency calibration module includes the steps of: Step S1, calculating a difference value between the count value SMP and a preset value CN to obtain a signed difference value wSMP; Step S2, calculating to obtain a corresponding adjustment quantity delta NFT according to the absolute value of the difference wSMP and the current control value NFT; Step S3, according to the sign of the difference wSMP, updating the control value NFT by using the adjustment quantity delta NFT; Step S4, calculating corresponding adjustment quantity delta RFT according to the absolute value of the difference wSMP and the current control value RFT; and S5, updating the control value RFT by using the adjustment quantity delt