CN-122026905-A - Dual-phase-locked loop-based working frequency adjustment method, processor and electronic equipment

CN122026905ACN 122026905 ACN122026905 ACN 122026905ACN-122026905-A

Abstract

The embodiment of the application provides a working frequency adjusting method based on a double phase-locked loop, a processor and electronic equipment, and relates to the field of integrated circuits. The method for adjusting the working frequency of the double phase-locked loop is used for adjusting the working frequency of a processor, the processor comprises a first phase-locked loop and a second phase-locked loop, the method for adjusting the working frequency of the double phase-locked loop comprises the steps of receiving an adjusting instruction for adjusting the working frequency of the processor, adjusting the second phase-locked loop based on the adjusting instruction when the first phase-locked loop provides a clock signal for the processor, wherein the first phase-locked loop is a current clock source of the processor, and switching the clock source of the processor from the first phase-locked loop to the second phase-locked loop after the second phase-locked loop is adjusted. The method is helpful for reducing abnormal conditions in the process of adjusting the working frequency of the processor.

Inventors

Ai Xueting
MA XIAO

Assignees

上海天数智芯半导体股份有限公司

Dates

Publication Date: 20260512
Application Date: 20250820

Claims (16)

1. The working frequency adjusting method based on the double phase-locked loops is characterized by being used for adjusting the working frequency of a processor, wherein the processor comprises a first phase-locked loop and a second phase-locked loop, and the first phase-locked loop and the second phase-locked loop are used for alternatively providing a clock signal for the processor so that the processor works at the working frequency corresponding to the clock signal; The working frequency adjusting method based on the double phase-locked loops comprises the following steps: receiving an adjustment instruction for adjusting the working frequency of the processor; Adjusting the second phase-locked loop based on the adjusting instruction under the condition that the first phase-locked loop provides a clock signal for the processor; And after the second phase-locked loop is adjusted, switching a clock source of the processor from the first phase-locked loop to the second phase-locked loop.
2. The dual phase locked loop based operating frequency adjustment method of claim 1, wherein the adjustment instruction comprises a target operating frequency required by the processor; The adjusting the second phase-locked loop based on the adjusting instruction under the condition that the first phase-locked loop provides a clock signal for the processor comprises the following steps: disabling the second phase locked loop if the first phase locked loop provides a clock signal to the processor; after the second phase-locked loop is unlocked, the frequency of the clock signal output by the second phase-locked loop is adjusted to be a target frequency, wherein the target frequency is the frequency of the clock signal required by the processor to work at the target working frequency; enabling the second phase-locked loop until the second phase-locked loop is locked.
3. The method of claim 2, wherein the adjustment instruction characterizes a type of adjustment of the operating frequency of the processor as an up-conversion; Before adjusting the second phase-locked loop based on the adjustment instruction, the method further comprises: And increasing the working voltage of the processor to the working voltage corresponding to the target working frequency.
4. The method for adjusting an operating frequency based on a dual phase locked loop as claimed in claim 3, wherein said adjusting said second phase locked loop based on said adjustment command after increasing an operating voltage of said processor to an operating voltage corresponding to said target operating frequency comprises: And if the working voltage is not stable, directly adjusting the second phase-locked loop based on the adjustment instruction under the state that the working voltage is not stable.
5. The method of claim 2, wherein the adjustment instruction characterizes a type of adjustment of the operating frequency of the processor as down-conversion; After switching the clock source of the processor from the first phase locked loop to the second phase locked loop, the method further comprises: And reducing the working voltage of the processor to a voltage corresponding to the target working frequency.
6. The method according to any one of claims 1-5, wherein the processor comprises a processing core, a connection architecture component, a cache, a memory controller and a memory which are sequentially connected, the processor further comprises a phase-locked loop connected with the processing core, the first phase-locked loop and the second phase-locked loop are used for alternatively connecting with the processing core and providing a clock signal for the processing core so that the processing core works at a working frequency corresponding to the clock signal; the method further comprises the steps of: In the process of switching the clock source of the processor from the first phase-locked loop to the second phase-locked loop, receiving a request of the processing core and the connection architecture component based on the cache and limiting the request to be sent to the memory controller so as to limit the processing core to call the memory.
7. The method of claim 6, wherein the cache and the memory controller are configured to control transmission of requests based on a predetermined credit mechanism, the credit mechanism comprising the cache allowing transmission of requests to the memory controller with a credit value; Before switching the clock source of the processor from the first phase locked loop to the second phase locked loop, the method further comprises: acquiring and storing the current configuration of the cache to the credit mechanism; after the credit mechanism is closed, the cache is limited to transmit a request to the memory controller; After switching the clock source of the processor from the first phase locked loop to the second phase locked loop, the cached credit mechanism is restored to the current configuration.
8. The method of claim 7, wherein the cache comprises a request buffer queue, and wherein the cache is configured such that after the cache is turned off the credit mechanism, the cache continues to receive requests sent by the processing core and the connection architecture component via the request buffer queue.
9. The dual phase locked loop based operating frequency adjustment method of claim 7 wherein the cache is configured to instruct the processing core to suspend request transmission after the request buffer queue is full of requests.
10. The dual phase-locked loop based operating frequency adjustment method of claim 7, wherein after controlling the cache to close the credit mechanism, before switching the clock source of the processor from the first phase-locked loop to the second phase-locked loop, the method further comprises: waiting for the processing core to enter an idle state, the idle state characterizing the processing core as being in a non-busy state.
11. The method of claim 7, wherein the adjustment instruction characterizes a type of adjustment of the operating frequency of the processor as an up-conversion, the adjustment instruction comprising a target operating frequency required by the processor; before adjusting the second phase-locked loop based on the adjustment instruction, the method further comprises the step of increasing the working voltage of the processor to the working voltage corresponding to the target working frequency; the method further includes waiting for the operating voltage to stabilize before obtaining and saving a current configuration of the credit mechanism by the cache.
12. A processor comprising a processor, a memory, and a control unit, characterized by comprising the following steps: A working module; A first phase-locked loop; A second phase-locked loop; The input end of the multiplexer is connected with the first phase-locked loop and the second phase-locked loop respectively, and the output end of the multiplexer is connected with the working module and is used for selecting one of the first phase-locked loop and the second phase-locked loop to provide a clock signal for the working module so that the working module works at a working frequency corresponding to the clock signal; The first phase-locked loop and the second phase-locked loop are used for being connected with a frequency modulation and voltage regulation module, the control end of the multiplexer is used for being connected with the frequency modulation and voltage regulation module, and the frequency modulation and voltage regulation module is used for executing the working frequency adjustment method based on the double phase-locked loops as claimed in any one of claims 1 to 11.
13. The processor of claim 12, wherein the processor is a general purpose graphics processor, GPGPU.
14. The processor of claim 12, wherein the processor comprises the fm voltage regulator module.
15. The processor of claim 12, wherein the fm voltage regulator module is a module that is independent of the processor.
16. An electronic device comprising a processor as claimed in any one of claims 12-15.

Description

Dual-phase-locked loop-based working frequency adjustment method, processor and electronic equipment Technical Field The application relates to the field of integrated circuits, and particularly provides a double-phase-locked loop-based working frequency adjustment method, a processor and electronic equipment. Background Currently, DVFS (Dynamic Voltage and Frequency Scaling, dynamically adjusting voltage and frequency) technology can dynamically adjust the operating frequency and power supply voltage of a processor according to the real-time load condition of the processor, so as to achieve the effects of reducing power consumption, improving the performance of the processor, and the like. The processing core in the processor controls the operating frequency by the clock signal provided by the phase-locked loop, so adjusting the operating frequency of the processor requires adjusting the phase-locked loop to change the clock signal output by the phase-locked loop. When the phase-locked loop is adjusted, the currently used clock source is required to be switched from the phase-locked loop to the reference clock, then the phase-locked loop is disabled to adjust the phase-locked loop in the disabled state, and the clock source is switched from the reference clock back to the phase-locked loop after the phase-locked loop is adjusted. Where the reference clock is typically a low frequency clock, for example, some reference clocks are 25MHz in frequency. And, the clock source may have a problem of 0 clock when switching between the phase locked loop and the reference clock, that is, a problem that the clock signal is 0 occurs in a short time. If a large number of tasks are issued to the processor by the upper layer application in the process of adjusting the working frequency, and operations such as calculation, data transmission, writing may be performed in each module of the processor, at this time, the frequency of the processor suddenly drops to be very low or even 0, which may cause abnormal problems such as system locking, data back pressure, data loss and the like of the processor. In some current solutions, the system clock input is turned off during frequency modulation, and turned on after the frequency modulation is completed, so as to solve the above problem. However, the task cannot be executed after the system clock is turned off, so that proper turn-off needs to be determined in advance, the task is controlled to be suspended, and the like, so that frequency modulation becomes more complex, and frequency modulation cannot be performed in time. Disclosure of Invention In view of the above, the present application is directed to a dual pll-based operating frequency adjustment method, a processor and an electronic device, so as to reduce abnormal problems occurring in the process of adjusting the operating frequency by the processor. In a first aspect, an embodiment of the present application provides a dual-phase-locked loop-based operating frequency adjustment method, configured to adjust an operating frequency of a processor, where the processor includes a first phase-locked loop and a second phase-locked loop, and the first phase-locked loop and the second phase-locked loop are configured to alternatively provide a clock signal for the processor, so that the processor operates at an operating frequency corresponding to the clock signal, where the dual-phase-locked loop-based operating frequency adjustment method includes receiving an adjustment instruction for adjusting the operating frequency of the processor, adjusting the second phase-locked loop based on the adjustment instruction when the first phase-locked loop provides the clock signal for the processor, where the first phase-locked loop is a current clock source of the processor, and switching the clock source of the processor from the first phase-locked loop to the second phase-locked loop after the second phase-locked loop adjustment is completed. In the embodiment of the application, two phase-locked loops, namely a first phase-locked loop and a second phase-locked loop, are arranged in a processor, when the working frequency needs to be adjusted, the first phase-locked loop is used as a clock source to normally output a clock signal, the second phase-locked loop adjusts the frequency of the output clock signal, and after the second phase-locked loop is adjusted, the clock source of the processor is switched from the first phase-locked loop to the second phase-locked loop. Compared with switching to the reference clock source, in the process, the first phase-locked loop can be used as the clock source to normally output the clock signal, so that the time of the processor at the low working frequency in the frequency modulation process is reduced, and the abnormal problem caused by the low working frequency in the frequency modulation process is reduced. Meanwhile, as the processor has clock input in the frequency modulation process and