CN-122026909-A - Digital-to-analog converter and pure digital domain calibration method thereof

CN122026909ACN 122026909 ACN122026909 ACN 122026909ACN-122026909-A

Abstract

The invention belongs to the technical field of mixed signal integrated circuits, and relates to a digital-to-analog converter and a pure digital domain calibration method thereof. The digital-to-analog converter comprises a calibration coefficient register, a decoder and a digital-to-analog conversion array, wherein the digital-to-analog conversion array adopts a segmented architecture and comprises a first segment of thermometer code DAC array, a second segment of binary code DAC array and a third segment of binary code DAC array, and the total weight of the third segment of binary code DAC array is enabled to be larger than the weight of the least significant bit of the second segment of binary code DAC array by adjusting the physical parameters of the first type unit device or the second type unit device, so that redundancy is provided for the second segment of binary code DAC array and the least significant bit of the first segment of thermometer code DAC array. The invention does not need to change the basic connection topology of the DAC, does not need to carry out the base conversion by a complex hardware multiplier or divider, ensures that the digital-to-analog converter obtains good precision and linearity, and can effectively improve the precision and linearity of the DAC.

Inventors

Liu Longren
SHI JIANCHENG
ZHANG MENGLIN
FAN CHAO
PU JIA

Assignees

成都振芯科技股份有限公司

Dates

Publication Date: 20260512
Application Date: 20260407

Claims (9)

1. A digital to analog converter, comprising: a calibration coefficient register for storing the calibration coefficient; The decoder is used for receiving the binary code value input by the digits and splitting the binary code value into a thermometer code value, a first binary code value and a second binary code value according to the calibration coefficient in the calibration coefficient register; the digital-to-analog conversion array is coupled to the decoder and used for generating an analog output voltage according to the thermometer code value, the first binary code value and the second binary code value; The digital-to-analog conversion array adopts a segmented architecture, and comprises: A first segment of thermometer code DAC array comprising a first type unit device for generating a first output component under control of thermometer code values; A second segment of binary code DAC array comprising a first type unit device for generating a second output component under control of the first binary code value; A third segment of binary code DAC array comprising a second type unit device for generating a third output component under control of the second binary code value; And adjusting physical parameters of the first type unit device or the second type unit device so that the sum of total weights of the third section of binary code DAC array is larger than the weight of the least significant bit of the second section of binary code DAC array, wherein the third section of binary code DAC array provides redundancy for the least significant bits of the second section of binary code DAC array and the first section of thermometer code DAC array.
2. The digital to analog converter of claim 1, wherein the physical parameters of the first type unit devices are adjusted by increasing resistance, decreasing capacitance, or decreasing current source, and wherein the physical parameters of the second type unit devices are adjusted by decreasing resistance, increasing capacitance, or increasing current source.
3. The digital-to-analog converter of claim 1, wherein the digital-to-analog converter is a resistive digital-to-analog converter, the first type unit device is a resistor of a first resistance, the second type unit device is a resistor of a second resistance, and the first resistance is greater than the second resistance such that a sum of voltage weights generated by the third segment of binary code DAC array is greater than a least significant bit weight of the second segment of binary code DAC array.
4. The digital to analog converter of claim 1, wherein the digital to analog converter is a capacitive digital to analog converter, the first type unit device is a capacitor of a first capacitance value, the second type unit device is a capacitor of a second capacitance value, the first capacitance value is unequal to the second capacitance value, and the first type unit device and the second type unit device are configured such that a total capacitance weight coverage of the third segment binary code DAC array exceeds a least significant bit step size of the second segment binary code DAC array.
5. The digital to analog converter of claim 1, wherein the digital to analog converter is a current source type digital to analog converter, the first type unit device is a current source of a first output current, the second type unit device is a current source of a second output current, the first output current is unequal to the second output current, and the first type unit device and the second type unit device are configured such that a total current output range of the third segment binary code DAC array is greater than a least significant bit current step size of the second segment binary code DAC array.
6. The digital-to-analog converter of claim 1, wherein the decoder re-encodes the digitally input binary code values based on the calibration coefficients stored in the calibration coefficient register.
7. A pure digital domain calibration method based on a digital-to-analog converter according to any of claims 1-6, comprising: The calibration coefficient register enters a calibration mode, and a control signal skips over the decoder to directly control a bit change-over switch of the digital-to-analog converter; determining a calibration start bit; measuring a reference state output voltage by placing all bit switches at a reference potential and measuring a first output voltage of the digital-to-analog converter at that time; measuring the actual weight bit by bit, namely switching a bit switching switch corresponding to a bit to be calibrated from a reference potential to a positive reference potential, and measuring a second stable output voltage; calculating and storing a calibration coefficient, namely calculating actual weight to be calibrated according to the difference value of the second output voltage and the first output voltage, calculating the calibration coefficient based on the actual weight and storing the calibration coefficient into a calibration coefficient register.
8. The pure digital domain calibration method based on the digital-to-analog converter of claim 7, wherein the measurement process of the same bit to be calibrated is repeatedly performed for a set number of times, and an average value of all measured differences between the second output voltage and the first output voltage is calculated as an actual weight of the bit to be calibrated.
9. The method for calibrating a pure digital domain based on a digital-to-analog converter as set forth in claim 7, wherein calculating the calibration coefficients based on the actual weights comprises setting the calibration coefficients to be , The first to be obtained for calibration The weight of the bit is determined by the bit weight, Is the ideal first The weight of the bit is determined by the bit weight, Is a positive integer and , Digital to analog converter bit weight number, then: 。

Description

Digital-to-analog converter and pure digital domain calibration method thereof Technical Field The invention belongs to the technical field of mixed signal integrated circuits, and particularly relates to a digital-to-analog converter and a pure digital domain calibration method thereof. Background In modern electronic systems, digital-to-Analog converters (DACs) are key interface circuits for connecting the Digital world and the Analog world, and are widely used in the fields of wireless communication, medical imaging, precision instruments and meters, audio processing, industrial control, and the like. With the continuous miniaturization and rapid improvement of digital signal processing capability of semiconductor process, the system has put more and more stringent demands on performance indexes of the DAC, in particular, resolution, precision, linearity and conversion speed. In an ideal case, the output voltage of the DAC should rise in a perfectly linear step with increasing input digital code. However, in practical integrated circuit manufacturing processes, due to random process fluctuations such as photolithography accuracy, etching rate, doping concentration gradients, and oxide thickness variations, there is inevitably a parameter mismatch in analog devices (e.g., resistor, capacitor, and current source transistors) that make up the DAC core array, resulting in deviation of the transfer function of the DAC from an ideal straight line, resulting in integral nonlinearity and differential nonlinearity errors. When the resolution of the DAC is required to reach 14 bits or higher, it has been difficult to ensure that the inherent matching accuracy of the devices meets the design requirements by only relying on matching techniques (such as common centroid layout and virtual device addition) in the analog circuit layout design. For example, under standard CMOS processing, an unmodified device match typically can only support about 10 to 12 bits of linearity. To achieve higher accuracy, trimming or calibration methods are generally employed. Conventional laser trimming is commonly used in resistive DACs to adjust the resistance by physically changing the geometry of the resistive material. However, the trimming method has obvious defects that firstly, the cost is high, the test time and the equipment investment are increased, secondly, the trimming is usually carried out in the wafer test stage, and parameter drift caused by mechanical stress in the subsequent packaging process cannot be eliminated, so that the upper limit of the precision is usually limited to about 16 bits. Digital calibration corrects for the non-linearities of the main DAC by compensating for parameter mismatch in the digital domain. In order for the digital calibration algorithm to work effectively, and in particular to calibrate large jump errors caused by high-order switching, the DAC architecture must have redundancy capability, ensuring that the transfer function of the DAC covers the entire output range without gaps, i.e. ensuring that the analog outputs of the DAC overlap between adjacent input code values. Existing DAC redundancy addition methods are typically implemented using non-binary weights, splitting binary weights, and inserting additional redundancy bits. These approaches, while effective, tend to result in extremely complex digital logic and increase the number of control lines and chip area of the analog array. Therefore, there is an urgent need for a solution that can effectively provide the amount of redundancy required for calibration without significantly increasing circuit complexity and chip area, and for an efficient pure digital domain calibration algorithm that fits the architecture. Disclosure of Invention In order to solve the above technical problems, the present invention provides a digital-to-analog converter and a pure digital domain calibration method thereof. In a first aspect, the present invention provides a digital to analog converter comprising: a calibration coefficient register for storing the calibration coefficient; The decoder is used for receiving the binary code value input by the digits and splitting the binary code value into a thermometer code value, a first binary code value and a second binary code value according to the calibration coefficient in the calibration coefficient register; the digital-to-analog conversion array is coupled to the decoder and used for generating an analog output voltage according to the thermometer code value, the first binary code value and the second binary code value; The digital-to-analog conversion array adopts a segmented architecture, and comprises: A first segment of thermometer code DAC array comprising a first type unit device for generating a first output component under control of thermometer code values; A second segment of binary code DAC array comprising a first type unit device for generating a second output component under control of the fi