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CN-122026912-A - Low-noise sample-and-hold circuit and method for successive approximation type ADC

CN122026912ACN 122026912 ACN122026912 ACN 122026912ACN-122026912-A

Abstract

The invention discloses a low-noise sampling hold circuit for a successive approximation type ADC and a sampling hold method thereof, which comprises a noise elimination sampling circuit with a capacitance multiplication circuit, wherein the output end of the noise elimination sampling circuit is sequentially connected with a comparator, an SAR logic control circuit and a sectional resistance DAC, and the input end of the noise elimination sampling circuit is respectively connected with sampling voltage and the output voltage of the sectional resistance DAC. The invention effectively eliminates the noise of the switch and the operational amplifier in the sample hold circuit through the charge sharing and the capacitance multiplication circuit, obviously reduces the equivalent input noise of the front end of the ADC, solves the problem that the operational amplifier has low noise, bandwidth and power consumption and is difficult to be compatible, and avoids the complex low-noise design of the operational amplifier of the main channel. The invention greatly improves the signal-to-noise ratio of the sample hold circuit, further improves the effective digit and quantization precision of the ADC system, and has the advantages of simple structure and easy realization.

Inventors

  • GUO ZHONGJIE
  • Xu Benzheng
  • GAO YUYANG
  • Bai Yina
  • DONG JIANFENG

Assignees

  • 西安理工大学

Dates

Publication Date
20260512
Application Date
20260126

Claims (10)

  1. 1. The low-noise sampling and holding circuit for the successive approximation type ADC is characterized by comprising a noise elimination sampling circuit comprising a capacitance multiplication circuit, wherein the output end of the noise elimination sampling circuit is sequentially connected with a comparator, an SAR logic control circuit and a sectional resistance DAC, and the input end of the noise elimination sampling circuit is respectively connected with sampling voltage and output voltage of the sectional resistance DAC.
  2. 2. The low noise sample and hold circuit for a successive approximation ADC of claim 1, wherein the noise cancellation sampling circuit comprises a capacitor Capacitance, capacitance One end of (a) is connected with a switch Switch Switch Switch Is connected with the sampling voltage at the other end Switch The other end of the capacitor is connected with the output voltage of the segmented resistor DAC Switch Switch with one end grounded and the other end grounded Is commonly connected with a capacitor at the other end Capacitance (capacitance) The other end of the voltage regulator is connected with an operational amplifier AMP1 and is connected with a non-inverting input end of the operational amplifier AMP1, and the non-inverting input end of the operational amplifier AMP1 is also connected with a resistor in turn And resistance of Resistance, resistance The other end of the output signal is connected to the output end of the operational amplifier AMP1, the output end of the operational amplifier AMP1 is connected to the inverting input end of the operational amplifier AMP1, and the output end of the operational amplifier AMP1 is also connected with a switch Switch And an operational amplifier AMP2 connected to its inverting input terminal, and a switch Is connected to the reference voltage at the other end Switch Is connected to the other end of the capacitor The non-inverting input terminal of the operational amplifier AMP2 is connected to the reference voltage The output end of the operational amplifier AMP2 is connected with a switch with the other end grounded And the other end is connected to the capacitor Switch at the other end The output of the op AMP2 is also connected to a comparator.
  3. 3. The low noise sample-and-hold circuit for a successive approximation ADC of claim 2, wherein the capacitance multiplication circuit is comprised of op-AMP 1, a resistor Resistance of resistor Capacitor A constitution in which N is a positive integer greater than 1, the operational amplifier AMP1 is used as a block operational amplifier to be in a unit gain negative feedback state, and the resistor is used for the feedback And resistance of The lower voltage level of (2) is the same voltage.
  4. 4. The low noise sample-and-hold circuit for a successive approximation ADC of claim 2, wherein the comparator comprises an op-AMP Pre-AMP having a forward input connected to an output of op-AMP 2, an inverting input of the op-AMP Pre-AMP being connected to a reference voltage The positive output end of the operational amplifier Pre-AMP is connected with a latch and is connected to the positive input end of the latch, the negative input end of the latch is connected to the negative output end of the operational amplifier Pre-AMP, and the output end of the latch is connected to the SAR logic control circuit.
  5. 5. The low noise sample and hold circuit for a successive approximation ADC of claim 2 wherein said segment resistor DAC comprises a high-order resistor string having a resistance passing through switches S1 through S # +1) Series-parallel connection is provided with a low-order resistance string, and the resistance on the low-order resistance string passes through a switch To the point of Is of the turn-on output voltage of (2) 。
  6. 6. The sample-and-hold method for a low noise sample-and-hold circuit of a successive approximation ADC of claim 2, comprising the steps of: Step 1, using a noise cancellation sampling circuit to input a signal to a sampling voltage Sequentially sampling, amplifying and charge sharing to obtain a voltage value with low noise coefficient ; Step 2, comparing the voltage values by using a comparator And segmented resistance DAC output voltage The comparison result is transmitted to the SAR logic control circuit; Step 3, controlling the output voltage of the segmented resistance DAC according to the comparison result by using the SAR logic control circuit Successive approximation quantization is repeated.
  7. 7. The sample-and-hold method for a low noise sample-and-hold circuit of a successive approximation ADC of claim 6, wherein said step 1 comprises the steps of: step 1.1, during sampling, the switch is controlled Switch Switch Closing while controlling the switch Switch Switch Switch Switch Disconnection, sampling capacitance For sampling voltage input signals Switch And a switch The operational amplifier AMP1 is in the working state, the operational amplifier AMP2 is not working, the capacitor No charge is stored; step 1.2, during amplification, control switch Switch Switch Closing while controlling the switch Switch Switch Switch Switch The break, the operational amplifier AMP1 and the operational amplifier AMP2 are in working state, the capacitor Storing the output voltage and noise of the operational amplifier AMP 2; Step 1.3, controlling the switch when charge sharing Switch Switch Closing while controlling the switch Switch Switch Switch Switch Disconnection, sampling capacitance And capacitor Connected in parallel and stored in the sampling capacitor And a capacitor The charge in the capacitor is shared to obtain a voltage value with low noise coefficient Meanwhile, the SAR logic control circuit and the segmented resistance DAC reset, and the capacitor is sampled Becomes the output voltage of the segmented resistance DAC 。
  8. 8. The sample-and-hold method of a low noise sample-and-hold circuit for a successive approximation ADC of claim 6, wherein in step 2, if the voltage value is Greater than the output voltage The comparator outputs a high level if the voltage value Less than the output voltage The comparator outputs a low level.
  9. 9. The sample-and-hold method of claim 6 wherein the SAR logic control circuit in step 3 controls the output voltage of the segment resistor DAC by controlling the on and off of the switches of the output voltage paths on the high-order resistor string and the low-order resistor string in the segment resistor DAC according to the level output by the comparator in step 2 Is of a size of (a) and (b).
  10. 10. The sample hold method of claim 6, wherein if the resolution of the ADC is L bits, repeating the steps 1 to 3 for L times, selecting the next approximated voltage value based on the output result of the comparator after each comparison, and generating 1 bit binary number according to the comparison result, and finally obtaining an L bit digital code as a primary conversion result.

Description

Low-noise sample-and-hold circuit and method for successive approximation type ADC Technical Field The invention belongs to the technical field of analog integrated circuit analog-to-digital converters, and particularly relates to a low-noise sample hold circuit for a successive approximation type ADC. The invention also relates to a low noise sample and hold method for a successive approximation ADC. Background With the rapid development of various electric tools using batteries, electric automobiles and other industrial products, the development of battery management chips is greatly promoted, the battery management chips have higher requirements on the sampling precision of battery voltage, the digital battery management chips need to use high-precision analog-to-digital converters (ADC), and circuit noise can deteriorate the overall precision of the ADC. As with any ADC with front-end S/H circuitry, the sampling noise of SAR ADCs can limit SNR. The traditional sampling hold circuit is composed of a sampling capacitor, an operational amplifier and an MOS switch, and adopts a lower-level plate sampling mode. In the sampling stage, the operational amplifier is connected into a unit gain negative feedback state, the upper plate of the sampling capacitor is clamped into a fixed voltage, the lower plate of the sampling capacitor is connected with an input signal, in the holding stage, the operational amplifier is in an open-loop state, the lower plate of the sampling capacitor is lifted along with the change of the input signal, the upper plate of the capacitor is always kept in charge conservation, and the upper plate lifts a voltage related to the input signal, so that the holding function is realized. However, in the sampling stage, noise of the operational amplifier and the switch can seriously pollute the charge of the upper plate of the capacitor, and the quantization precision of the ADC is affected. Aiming at the problems, the low-noise operational amplifier can be used for sampling and holding the input signal, but the operational amplifier has too high requirement, the design difficulty is increased, and the noise of the MOS switch tube cannot be eliminated. The low noise index of the operational amplifier is contrary to the indexes such as bandwidth, power consumption, slew rate and the like, the main operational amplifier of the sample hold circuit is positioned on the main channel of the ADC, the indexes such as gain and bandwidth of the main operational amplifier can seriously influence the performance of the whole system, and the low noise processing of the operational amplifier of the main channel is difficult to realize. Disclosure of Invention The invention aims to provide a low-noise sample hold circuit for a successive approximation type ADC, which solves the problem that the prior sample hold circuit is influenced by circuit noise to cause the deterioration of effective digits. It is another object of the invention to provide a low noise sample and hold method for a successive approximation ADC. The first technical scheme adopted by the invention is that the low-noise sampling and holding circuit for the successive approximation type ADC comprises a noise elimination sampling circuit comprising a capacitance multiplication circuit, wherein the output end of the noise elimination sampling circuit is sequentially connected with a comparator, an SAR logic control circuit and a sectional resistance DAC, and the input end of the noise elimination sampling circuit is respectively connected with a sampling voltage and the output voltage of the sectional resistance DAC. The first technical solution of the invention is also characterized in that, The noise cancellation sampling circuit comprises a capacitorCapacitance, capacitanceOne end of (a) is connected with a switchSwitchSwitchSwitchIs connected with the sampling voltage at the other endSwitchThe other end of the capacitor is connected with the output voltage of the segmented resistor DACSwitchSwitch with one end grounded and the other end groundedIs commonly connected with a capacitor at the other endCapacitance (capacitance)The other end of the voltage regulator is connected with an operational amplifier AMP1 and is connected with a non-inverting input end of the operational amplifier AMP1, and the non-inverting input end of the operational amplifier AMP1 is also connected with a resistor in turnAnd resistance ofResistance, resistanceThe other end of the output signal is connected to the output end of the operational amplifier AMP1, the output end of the operational amplifier AMP1 is connected to the inverting input end of the operational amplifier AMP1, and the output end of the operational amplifier AMP1 is also connected with a switchSwitchAnd an operational amplifier AMP2 connected to its inverting input terminal, and a switchIs connected to the reference voltage at the other endSwitchIs connected to the other end of the capacitorThe no