CN-122026913-A - Bipolar voltage time converter based on inverter threshold detection

CN122026913ACN 122026913 ACN122026913 ACN 122026913ACN-122026913-A

Abstract

The invention discloses a bipolar voltage time converter based on inverter threshold detection, which comprises a differential sampling circuit, a sign bit comparator, a bipolar voltage-time conversion circuit, a common mode feedback circuit and an inverter threshold detection circuit, wherein the sign bit comparator is used for receiving differential sampling voltage output by the differential sampling circuit, judging the polarity of an input differential analog signal, connecting the differential sampling circuit with the bipolar voltage-time conversion circuit, outputting a sign bit signal and a polarity control signal, the bipolar voltage-time conversion circuit is used for charging or discharging the differential sampling voltage under the control of the polarity control signal to generate two paths of voltage ramp signals with opposite polarities, the common mode feedback circuit is connected with the inverter threshold detection circuit, the common mode feedback circuit is used for detecting the common mode level of the differential sampling voltage or the two paths of voltage ramp signals, and the threshold voltage of the inverter threshold detection circuit is configured to be a preset common mode level and used for detecting the crossing event of the two paths of voltage ramp signals at the preset common mode level and outputting a threshold detection signal.

Inventors

YIN YONGSHENG
LIN KAIWEN
DENG HONGHUI
TAO CHENGHAO
LIU HAO
YANG YI

Assignees

合肥工业大学

Dates

Publication Date: 20260512
Application Date: 20260204

Claims (7)

1. The bipolar voltage time converter based on the inverter threshold detection is characterized by comprising a differential sampling circuit, a sign bit comparator, a bipolar voltage-time conversion circuit, a common mode feedback circuit and an inverter threshold detection circuit; the output end of the differential sampling circuit is connected to the input end of the sign bit comparator and the input end of the bipolar voltage-time conversion circuit; The symbol bit comparator is used for receiving the differential sampling voltage output by the differential sampling circuit, judging the polarity of the input differential analog signal, and the output end of the symbol bit comparator is connected to the control end of the bipolar voltage-time conversion circuit to output a symbol bit signal and a polarity control signal; The bipolar voltage-time conversion circuit is used for charging or discharging the differential sampling voltage under the control of the polarity control signal to generate two paths of voltage ramp signals with opposite polarities, and the output end of the bipolar voltage-time conversion circuit is connected to the input end of the common mode feedback circuit and the input end of the inverter threshold detection circuit; The common mode feedback circuit is used for detecting the common mode level of the differential sampling voltage or the two voltage ramp signals, the output end of the common mode feedback circuit is connected to the bias adjusting end of the current source in the bipolar voltage-time conversion circuit, and the common mode level of the intersection point of the two voltage ramp signals is kept at a preset common mode level by adjusting the bias voltage; The threshold voltage of the inverter threshold detection circuit is configured to the predetermined common mode level for detecting a crossing event of the two-way voltage ramp signal at the predetermined common mode level and outputting a threshold detection signal.
2. The bipolar voltage to time converter based on inverter threshold detection of claim 1 wherein the sign bit comparator comprises a pre-charge circuit, an input boost circuit, a regenerative latch circuit, and an output buffer circuit; the pre-charging circuit comprises a PMOS tube P3 and a PMOS tube P4, wherein the sources of the PMOS tube P3 and the PMOS tube P4 are connected with power supply voltage, the gates are connected with clock signals, and the drains are respectively connected to a node X and a node Y; The input enhancement circuit comprises an NMOS tube N1, an NMOS tube N2, an NMOS tube N3, an NMOS tube N4 and an NMOS tube N7, wherein the grid electrode of the NMOS tube N1 is connected with a positive input signal, the drain electrode of the NMOS tube N1 is connected with a node X, and the source electrode of the NMOS tube N3 is connected with the drain electrode of the NMOS tube N3; The regeneration latch circuit comprises a PMOS tube P1, a PMOS tube P2, a PMOS tube P5, a PMOS tube P6, an NMOS tube N5, an NMOS tube N6, an NMOS tube N8, an NMOS tube N9 and an NMOS tube N10, wherein the sources of the PMOS tube P1 and the PMOS tube P2 are connected with power supply voltages, the drains are respectively connected to a node X and a node Y, the sources of the PMOS tube P5 and the PMOS tube P6 are connected with the power supply voltages, the gates of the P5 are connected to the node X, the gates of the P6 are connected to the node Y, the sources of the NMOS tube N9 and the NMOS tube N10 are grounded, the gates of the NMOS tube N9 and the NMOS tube N10 are connected with an inverted clock signal, the gates of the PMOS tube P1 are connected to a communication node between the drains of the PMOS tube P5 and the drains of the NMOS tube N9, the gates of the NMOS tube P2 are connected to a communication node between the drains of the PMOS tube P6 and the drains of the NMOS tube N10, the drains of the NMOS tube N5 are connected to the node X, the gates of the NMOS tube N6 are connected to the node Y, the drains of the NMOS tube N6 are connected to the node Y, the gates of the NMOS tube N5 are connected to the node X, the drains of the common drain of the NMOS tube N8 is connected to the drain of the drain tube N8; The output buffer circuit includes an inverter connected between the node X and the output terminal Vop, and an inverter connected between the node Y and the output terminal Von.
3. The bipolar voltage-to-time converter based on inverter threshold detection of claim 1 wherein the bipolar voltage-to-time conversion circuit comprises a positive side sampling capacitor Csp, a negative side sampling capacitor Csn, a P-type cascode current source, an N-type cascode current source, a switching network, and a reset switch; The P-type cascode current source consists of a PMOS tube P7 and a PMOS tube P8 which are connected in series, wherein the source electrode of the PMOS tube P7 is connected with a power supply voltage, the drain electrode of the PMOS tube P7 is connected with the source electrode of the PMOS tube P8, and the grid electrodes of the PMOS tube P7 and the PMOS tube P8 are respectively connected with corresponding bias voltages; The N-type common-source and common-gate current source consists of an NMOS tube N13 and an NMOS tube N14 which are connected in series, wherein the source electrode of the NMOS tube N14 is grounded, the drain electrode of the NMOS tube N14 is connected with the source electrode of the NMOS tube N13, the grid electrode of the NMOS tube N13 is connected with a corresponding bias voltage, and the grid electrode of the NMOS tube N14 is connected with a common-mode feedback output dynamic bias end; The switch network comprises a PMOS tube P9, a PMOS tube P10, an NMOS tube N11 and an NMOS tube N12, wherein the grid electrode of a transistor in the switch network is connected with a polarity control signal, the drain electrode of the PMOS tube P8 is respectively connected with the source electrodes of the PMOS tube P9 and the PMOS tube P10, the drain electrode of the NMOS tube N13 is respectively connected with the source electrodes of the NMOS tube N11 and the NMOS tube N12, the drain electrodes of the PMOS tube P9 and the NMOS tube N11 are commonly connected with the positive end sampling capacitor Csp, and the drain electrode of the PMOS tube P10 and the drain electrode of the NMOS tube N12 are commonly connected with the negative end sampling capacitor Csn; The reset switch comprises a PMOS tube P11 and an NMOS tube N15 which are connected in parallel between the positive end sampling capacitor Csp and the negative end sampling capacitor Csn, and the grid electrodes of the PMOS tube P11 and the NMOS tube N15 are connected with a reset control signal for communicating the positive end sampling capacitor Csp and the negative end sampling capacitor Csn in a reset stage.
4. A bipolar voltage time converter based on inverter threshold detection as claimed in claim 3 wherein the switching network is controlled by the polarity control signal: When the positive end sampling capacitor Csp needs to be discharged and the negative end sampling capacitor Csn needs to be charged, the PMOS transistor P10 and the NMOS transistor N11 are turned on; When the positive side sampling capacitor Csp needs to be charged and the negative side sampling capacitor Csn needs to be discharged, the PMOS transistor P9 and the NMOS transistor N12 are turned on.
5. The bipolar voltage to time converter of claim 1 wherein the common mode feedback circuit is a switched capacitor common mode feedback circuit comprising capacitor C1, capacitor C2, capacitor C3, capacitor C4, switch SW1, switch SW2, switch SW3, switch SW4, switches SW5 and SW6; the switch is controlled by a first clock phase Φ1 and a second clock phase Φ2: When the first clock phase phi 1 is adopted, a switch SW1, a switch SW2 and a switch SW3 are turned on, and a switch SW4, a switch SW5 and a switch SW6 are turned off, wherein the switch SW1 connects an upper polar plate of a capacitor C1 to a common mode reference voltage VCM, the switch SW2 commonly connects a lower polar plate of the capacitor C1 and an upper polar plate of the capacitor C2 to a bias voltage VBIAS, and the switch SW3 connects a lower polar plate of the capacitor C2 to the common mode reference voltage VCM; In the second clock phase phi 2, a switch SW4, a switch SW5 and a switch SW6 are turned on, a switch SW1, a switch SW2 and a switch SW3 are turned off, the switch SW4 connects an upper polar plate of a capacitor C1 to a positive output end VOP, the switch SW5 connects a lower polar plate of the capacitor C1 and an upper polar plate of the capacitor C2 to a bias adjustment end VCMFB together, the switch SW6 connects a lower polar plate of the capacitor C2 to a negative output end VON, the capacitor C3 is connected between the positive output end VOP and the bias adjustment end VCMFB, and the capacitor C4 is connected between the bias adjustment end VCMFB and the negative output end VON.
6. The bipolar voltage to time converter of claim 5 wherein the common mode feedback circuit adjusts the voltage of the VCMFB via capacitive charge sharing to control the current of the current source in the bipolar voltage to time converter circuit to stabilize the output common mode level at the common mode reference voltage VCM.
7. The bipolar voltage-to-time converter based on inverter threshold detection according to claim 1, wherein the inverter threshold detection circuit comprises a CMOS inverter composed of a PMOS transistor P12 and an NMOS transistor N16 connected in series, the gates of the PMOS transistor P12 and the NMOS transistor N16 are commonly connected as an input terminal and connected to an output terminal of the bipolar voltage-to-time conversion circuit, the drains are commonly connected as an output terminal and output the threshold detection signal, and the aspect ratio of the PMOS transistor P12 and the NMOS transistor N16 is configured such that the inversion threshold voltage of the CMOS inverter is equal to the predetermined common mode level.

Description

Bipolar voltage time converter based on inverter threshold detection Technical Field The invention belongs to the technical field of power electronics, and particularly relates to a bipolar voltage time converter based on inverter threshold detection. Background With the development of high-speed serial interfaces and high-bandwidth communication systems, a receiver architecture of an analog-to-digital converter (ADC) +digital signal processing is widely adopted at a receiving end. Although such application scenarios have only medium and low precision requirements on the ADC, in order to better realize GS/s-magnitude high-rate data transmission, the ADC is often required to realize high sampling rate and good energy efficiency under the condition of compact area. Successive Approximation (SAR) and pipelined (Pipeline) ADCs of the traditional voltage domain show advantages in medium sampling rate and medium-high resolution scenarios. However, under the conditions of submicron process nodes and high sampling rate, it is difficult for the front-end sampling and voltage comparison circuit to simultaneously achieve both accuracy and speed. Although the performance of the existing mixed architecture ADC is improved, if only the voltage domain ADC is used as a sub-stage, the limitation of power consumption and area is still faced, and the introduction of the high-performance interstage amplifier also increases the complexity of circuit design. Aiming at the bottleneck faced by the voltage domain signal processing under the submicron process, the time domain analog-to-digital conversion technology provides an effective solution. In advanced processes, a reduction in the supply voltage results in a limited dynamic range of the voltage domain signal, while the transmission delay of the transistor decreases with shrinking process dimensions. The time quantization accuracy and speed of a time-to-digital converter (TDC) are mainly affected by the flip speed of the logic gate, and this physical property makes the accuracy and speed performance of the TDC exhibit an increasing trend under advanced process nodes. The TDC transfers signal processing from an increasingly limited voltage domain to a time domain which can benefit from process miniaturization, particularly under the application background of medium and low precision and high sampling rate, the TDC not only shows the architecture advantage of high digitization, but also reduces power consumption and area overhead while realizing ultrahigh-speed conversion due to the characteristic of no need of high-gain operational amplification. The TDC is introduced into the mixed architecture ADC as a sub-stage, so that the limitation of power consumption-speed compromise faced by the full-voltage domain cascade architecture when the conversion rate is increased is overcome. Compared with adopting a Flash or SAR equal-voltage domain ADC as a sub-stage, the TDC is used as the sub-stage to carry out fine quantization, so that dependence on a high-bandwidth residual error amplifier or a high-speed comparator is avoided. The mixed architecture ADC fully combines the high linearity of voltage domain coarse quantization and the high-speed and low-power consumption characteristics of time domain fine quantization, and can realize higher energy efficiency on the premise of ensuring high sampling rate. In the TDC, in order to expand the dynamic range and improve the linearity, a bipolar voltage-time converter (BVTC) is often adopted, wherein the sampled differential voltage forms voltage slopes with opposite polarities in a two-path structure, and the slope crossing time is transmitted to the TDC, so that the mapping from voltage to time is realized. In conventional architecture, cross detection is typically achieved by a zero-cross detector (ZCD). ZCD is typically composed of multiple differential amplifiers and regenerative latch stages, requiring amplification of very small differential signals near the crossover, which has the following drawbacks: 1. The detection delay is larger, namely larger delay is introduced in the multistage analog amplification and regeneration process, so that the ADC sampling rate is limited; 2. The input common mode range of ZCD is limited, the common mode level of BVTC output voltage slopes has stronger dependence, and when the common mode level drifts or deviates from the expected, the detection precision is reduced; 3. The circuit is complex, the area consumption is high, and the multi-stage amplifying and biasing circuit is needed to obtain enough gain and bandwidth, so that the high power consumption and area are consumed. On the other hand, most of traditional BVTC only charges and discharges the sampling capacitor through the current source to form a voltage slope, and the common mode level lacks effective control, so that the common mode level of the intersection point of the two paths of voltage slopes drifts along with process, temperature, p