CN-122026915-A - Dynamic comparator and time sequence control method thereof

CN122026915ACN 122026915 ACN122026915 ACN 122026915ACN-122026915-A

Abstract

The application discloses a dynamic comparator and a time sequence control method thereof, wherein the dynamic comparator comprises a chopper, a dynamic pre-amplifier, a charge redistribution circuit and a latch; the chopper inputs differential input signals, outputs positive-phase connection output signals and reverse-phase connection output signals of the differential input signals in a time-sharing mode, the dynamic pre-amplifier sequentially amplifies the positive-phase connection output signals and the reverse-phase connection output signals, stores first differential signals amplified by the positive-phase connection output signals into a first capacitor array, stores second differential signals amplified by the reverse-phase connection output signals into a second capacitor array, the charge redistribution circuit is used for combining the first differential signals and the second differential signals in the capacitor array and outputting pre-amplified differential analog voltages to the latch, and the latch is used for outputting comparison results according to the pre-amplified differential analog voltages and keeping the comparison results to the next period. The scheme of the application can reduce offset voltage and output common mode offset while meeting the requirement of high energy efficiency ratio.

Inventors

FAN XINHAO
ZHANG HAO
YANG YAGUANG
CHEN LIPING
ZHAO KUN

Assignees

中国科学院微电子研究所

Dates

Publication Date: 20260512
Application Date: 20260204

Claims (10)

1. The dynamic comparator is characterized by comprising a chopper, a dynamic pre-amplifier, a charge redistribution circuit and a latch, wherein the charge redistribution circuit comprises a first capacitor array and a second capacitor array which are formed by a plurality of capacitors; The chopper is used for inputting differential input signals and outputting a positive phase connection output signal and an inverse phase connection output signal of the differential input signals in a time-sharing manner; The dynamic pre-amplifier is used for amplifying the forward-phase output signal and the reverse-phase output signal output by the chopper in sequence, storing a first differential signal amplified by the forward-phase output signal into the first capacitor array, and storing a second differential signal amplified by the reverse-phase output signal into the second capacitor array; the charge redistribution circuit is configured to combine the first differential signal in the first capacitor array and the second differential signal in the second capacitor array, and output a pre-amplified differential analog voltage to the latch; The latch is used for outputting a comparison result according to the pre-amplified differential analog voltage and keeping the comparison result until the next period, and the comparison result is a digital differential signal.
2. The dynamic comparator of claim 1, wherein the dynamic pre-amplifier comprises a first control module, a storage capacitor, an amplifier; the energy storage capacitor is controlled by the first control module and is used for charging to the power supply voltage in a reset stage; The amplifier is controlled by the first control module and is used for amplifying the forward-phase method output signal and the reverse-phase method output signal output by the chopper in sequence in an amplifying stage, storing a first differential signal amplified by the forward-phase method output signal into the first capacitor array, and storing a second differential signal amplified by the reverse-phase method output signal into the second capacitor array.
3. The dynamic comparator of claim 2, wherein the storage capacitor comprises a first capacitor and a second capacitor; In an amplifying stage of the positive phase method output signal, the first capacitor supplies power to the amplifier; the second capacitor supplies power to the amplifier during an amplification stage of the inverted output signal.
4. The dynamic comparator of claim 3, wherein the first control module comprises a first charge control unit, a second charge control unit, a first discharge control unit, and a second discharge control unit; in a reset phase, the first charge control unit and the second charge control unit are closed, and the first discharge control unit and the second discharge control unit are opened, so that a power supply charges the first capacitor and the second capacitor; In the amplifying stage of the positive phase method output signal, the first charging control unit is opened, the first discharging control unit is closed, the second discharging control unit is opened, the first capacitor supplies power to the amplifier, and the amplifier stores a first differential signal amplified by the positive phase method output signal into the first capacitor array; and in the amplification stage of the reverse phase connection output signal, the second charge control unit is disconnected, the first discharge control unit is disconnected, the second discharge control unit is closed, the second capacitor supplies power to the amplifier, and the amplifier stores a second differential signal amplified by the reverse phase connection output signal into the second capacitor array.
5. The dynamic comparator of claim 2, wherein the dynamic pre-amplifier further comprises: And the first reset module is used for resetting the output end of the amplifier after the amplifier finishes amplifying the positive phase connection output signal or the reverse phase connection output signal output by the chopper.
6. The dynamic comparator of claim 5, wherein the first reset module comprises two reset switches, one of which is connected between the positive output of the amplifier and a set voltage, and the other of which is connected between the negative output of the amplifier and the set voltage.
7. The dynamic comparator of claim 2, wherein the charge redistribution circuit comprises a positive phase output and a negative phase output, further comprising a first switch array and a second switch array, the first switch array comprising a plurality of merged switches, each merged switch connecting a capacitor in the charge redistribution circuit, the second switch array comprising two reset switches, one reset switch connected between the positive phase output and a set voltage, the other reset switch connected between the negative phase output and the set voltage; in the amplifying stage, each merging switch in the first switch array is opened, and each reset switch in the second switch array is closed; after the amplification process is completed, each merging switch in the first switch array is closed, and each reset switch in the second switch array is opened.
8. A method for timing control of a dynamic comparator, the method comprising: The method comprises the steps of outputting a positive-phase method output signal and an inverse-phase method output signal of differential input signals in a time-sharing mode, amplifying the positive-phase method output signal and the inverse-phase method output signal in sequence, and storing a first differential signal amplified by the positive-phase method output signal and a second differential signal amplified by the inverse-phase method output signal into a capacitor array; combining the first differential signal and the second differential signal in the capacitor array to obtain a pre-amplified differential analog voltage; And outputting a comparison result according to the pre-amplified differential analog voltage.
9. The method of timing control of a dynamic comparator according to claim 8, wherein the capacitor array comprises a first capacitor array and a second capacitor array, and the number and the size of the capacitors in the first capacitor array and the second capacitor array are the same; The storing the first differential signal amplified by the positive-phase output signal and the second differential signal amplified by the negative-phase output signal into a capacitor array includes: Storing a first differential signal amplified by the positive phase method output signal into the first capacitor array; and storing a second differential signal amplified by the inverse connection output signal into the second capacitor array.
10. The timing control method of a dynamic comparator according to claim 8, wherein the method further comprises: amplifying the positive phase connection output signal and the negative phase connection output signal in sequence comprises: Amplifying the output signal of the positive phase connection method, resetting and amplifying the output signal of the negative phase connection method.

Description

Dynamic comparator and time sequence control method thereof Technical Field The application relates to the field of electronic circuits, in particular to a dynamic comparator and a time sequence control method thereof. Background With the continuous development of high-speed analog-to-digital converters, image sensor readout circuits and precision analog signal processing systems, comparators serve as important interfaces between analog and digital signals, and their performance directly affects the resolution, power consumption, speed, etc. of the overall system. The conventional function of a comparator is to compare and decide on analog signals, in particular in analog-to-digital converters, the magnitude of an input signal and a digital-to-analog converter (DAC) output signal or a reference signal. How to balance and optimize the noise performance, the power consumption level and the decision speed of the comparator is always a design difficulty and a hot spot in the related art. The mainstream architecture of the comparator takes the form of a cascade of pre-amplifiers and latches, both for a compromise in speed and noise performance. The pre-amplifier may be single stage or multi-stage for amplifying the input signal prior to latch decision so that the tiny input signal is amplified to a magnitude sufficient for the latch to regenerate quickly. The latch, which is usually one stage only and placed at the end, rapidly makes decisions on the signal and outputs a digital signal in a form similar to positive feedback, and too small an input signal amplitude is detrimental to the reproduction speed. From the perspective of noise and offset voltage analysis, the structure of the pre-amplifier is beneficial to reducing equivalent input noise and offset voltage of the comparator, and offset voltage and partial low-frequency noise can be eliminated at the pre-amplifier stage through self-zeroing and other technologies. Comparators can be broadly divided into conventional pre-amplifier structures and new dynamic amplifier structures, depending on the type of pre-amplifier. The prior art has the defects that 1, a traditional comparator structure adopts a static bias pre-amplifier, and the energy efficiency ratio is too low under the indexes of the same noise and speed performance. 2. The comparator based on the dynamic amplifier as the pre-amplifier cannot effectively process the input offset voltage and the output common mode offset, so that the structural comparator is difficult to reach high-precision design indexes at the same design speed. Disclosure of Invention The embodiment of the application provides a dynamic comparator and a time sequence control method thereof, so that the problem that the comparator based on a dynamic pre-amplifier cannot effectively process offset voltage and output common mode offset is solved while the high energy efficiency ratio is met. In one aspect, the embodiment of the application provides a dynamic comparator, which comprises a chopper, a dynamic pre-amplifier, a charge redistribution circuit and a latch, wherein the charge redistribution circuit comprises a first capacitor array and a second capacitor array which are formed by a plurality of capacitors; The chopper is used for inputting differential input signals and outputting a positive phase connection output signal and an inverse phase connection output signal of the differential input signals in a time-sharing manner; The dynamic pre-amplifier is used for amplifying the forward-phase output signal and the reverse-phase output signal output by the chopper in sequence, storing a first differential signal amplified by the forward-phase output signal into the first capacitor array, and storing a second differential signal amplified by the reverse-phase output signal into the second capacitor array; the charge redistribution circuit is configured to combine the first differential signal in the first capacitor array and the second differential signal in the second capacitor array, and output a pre-amplified differential analog voltage to the latch; The latch is used for outputting a comparison result according to the pre-amplified differential analog voltage and keeping the comparison result until the next period, and the comparison result is a digital differential signal. Optionally, the dynamic pre-amplifier comprises a first control module, a storage capacitor and an amplifier; the energy storage capacitor is controlled by the first control module and is used for charging to the power supply voltage in a reset stage; The amplifier is controlled by the first control module and is used for amplifying the forward-phase method output signal and the reverse-phase method output signal output by the chopper in sequence in an amplifying stage, storing a first differential signal amplified by the forward-phase method output signal into the first capacitor array, and storing a second differential signal amplified by the reverse-