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CN-122026916-A - LC-SAR combined DAC structure with ARRM modules applied to LC ADC and working method thereof

CN122026916ACN 122026916 ACN122026916 ACN 122026916ACN-122026916-A

Abstract

The invention provides an LC-SAR combined DAC structure with ARRM modules applied to an LC ADC and a working method thereof, comprising the LC-SAR combined DAC module, an LC quantization loop module, an SAR quantization loop module and a self-adaptive reset reference voltage source module ARRM, wherein coarse and fine two-stage quantization is realized by fusing the LC DAC and the SAR DAC, and residual injection is realized by introducing the self-adaptive reset reference voltage source module, so that quantization errors caused by loop delay are effectively compensated on the premise of not increasing system power consumption, signal reconstruction waveform distortion is reduced, and the integral quantization precision of the LC ADC is greatly improved.

Inventors

  • HU WEI
  • Tu Haowen
  • JI MINGZHI
  • CHEN ZEJIE
  • WU ZHIXIAO
  • LIANG BIN

Assignees

  • 福州大学

Dates

Publication Date
20260512
Application Date
20260410

Claims (10)

  1. 1. The LC-SAR combined DAC structure with ARRM modules applied to the LC ADC is characterized by comprising an LC-SAR combined DAC module, an LC quantization loop module, an SAR quantization loop module and an adaptive reset reference voltage source module ARRM, wherein the LC-SAR combined DAC module is connected with the LC quantization loop module and the SAR quantization loop module, the LC quantization loop module is connected with the SAR quantization loop module, and the adaptive reset reference voltage source module ARRM is connected with the LC-SAR combined DAC module, the LC quantization loop module and the SAR quantization loop module; The input end of the LC-SAR combined DAC module receives an analog input signal V IN , a reference voltage V REF , a common mode level V CM , a thermometer code DLCT <14:1>, a binary code DSAR <4:1>, an enable signal EN and a reset signal RST, and the output end of the LC-SAR combined DAC module transmits an output signal V M ; The input end of the LC quantization loop module receives an output signal V M , a common mode level V CM , a high threshold voltage V H and a low threshold voltage V L , and the output end of the LC quantization loop module outputs a thermometer code DLCT <14:1>, a crossing signal TCROSS and an enable signal EN; The input end of the SAR quantization loop module receives an output signal V M , a common mode level V CM and a traversing signal TCROSS, and the output end of the SAR quantization loop module outputs a binary code DSAR <4:1>, a reset signal RST and a quantization completion signal CMPOK; The input of the adaptive reset reference voltage source module ARRM receives thermometer code DLCT <14:1>, reset signal RST, and quantization completion signal CMPOK, and the output of the adaptive reset reference voltage source module ARRM outputs reference voltage V REF .
  2. 2. The LC-SAR combined DAC structure with ARRM module for LC ADC as claimed in claim 1, wherein the circuit structure of the LC-SAR combined DAC module comprises an input capacitor C IN , an array of SAR DAC capacitors, The LC DAC capacitor array and the output end, wherein the upper polar plate of the input capacitor C IN is connected with an analog input signal V IN , the lower polar plate of the input capacitor C IN is used as a core common connection node which is connected with the upper polar plates of all capacitors of the SAR DAC capacitor array to realize common-point electric connection, meanwhile, the common connection node is also a signal coupling node of the LC DAC capacitor array to realize the partial pressure transmission of the analog input signal V IN to the SAR DAC capacitor array and the LC DAC capacitor array, the LC DAC capacitor array comprises an enabling switch SW1, two ends of the enabling switch SW1 are respectively connected with the analog input signal V IN and the upper polar plate of the input capacitor C IN , the enabling switch SW1 is controlled by an enabling signal EN, and the LC capacitor array further comprises a reset switch SW2, A reset switch SW3, a reset switch SW2, The reset switch SW3 is controlled by a reset signal RST, two ends of the reset switch SW2 are respectively connected with a reference voltage V REF and an upper polar plate of the input capacitor C IN , two ends of the reset switch SW3 are respectively connected with a common mode level V CM and a lower polar plate of the input capacitor C IN , and an output end of the LC-SAR combined DAC module is connected with the LC quantization loop module and the SAR quantization loop module and is used for transmitting an output signal V M .
  3. 3. The LC-SAR combined DAC structure with ARRM module for LC ADC as claimed in claim 2, wherein said SAR DAC capacitor array is composed of several binary weighted capacitors as fine quantized core capacitor unit, the upper electrode plate of all binary weighted capacitors is connected with the common connection node of the lower electrode plate of input capacitor C IN , the lower electrode plate of each binary weighted capacitor is independently connected with two switches, the other side of the two switches is respectively connected with power voltage V DD and ground V SS to realize the lower electrode plate potential switching of binary weighted capacitor controlled by the code value of binary code DSAR <4:1 >; The LC DAC capacitor array consists of a plurality of thermometer code weight capacitors which are coarse quantization core capacitor units, wherein the upper polar plates of all the thermometer code weight capacitors are connected to a common connection node of the SAR DAC capacitor array and an input capacitor C IN , the lower polar plate of each thermometer code weight capacitor is independently connected with two other switches, and the other sides of the two switches are respectively connected with a power supply voltage V DD and a ground voltage V SS so as to realize the potential switching of the lower polar plate of the thermometer code weight capacitor controlled by the thermometer code DLCT <14:1> code value.
  4. 4. The LC-SAR combined DAC architecture with ARRM module for LC ADC according to claim 3, wherein the adaptive reset reference voltage source module ARRM comprises a thermometer code binary circuit, a delay unit, a 4-16 decoder and a multiplexing switch, wherein the output of the thermometer code binary circuit and the delay unit are connected to the input of the 4-16 decoder, the output of the 4-16 decoder is connected to the multiplexing switch for outputting multiplexing switch control signals Y <15:0>, the multiplexing switch is connected to the reset switch SW2 of the LC-SAR combined DAC module for outputting a reference voltage source V REF , the input of the thermometer code binary circuit is connected to the SAR quantization loop module for receiving a quantization completion signal CMPOK, the input of the delay unit is connected to the SAR quantization loop module for receiving a reset signal RST, and the input of the thermometer code binary circuit is connected to the LC quantization loop module for receiving a thermometer code <14:1>.
  5. 5. The LC-SAR combined DAC architecture with ARRM module for use in an LC ADC as claimed in claim 4, wherein the LC quantization loop module comprises a first comparator, a second comparator, a selector, an XD, UD logic, a shift register, an or logic, and an EN logic; The output of the first comparator is connected with XD and UD logic, the XD and UD logic is connected with a selector, or logic and a shift register, the selector is connected with the input of the second comparator, the output of the second comparator is connected with the shift register, or logic is connected with EN logic, the shift register is connected with an LC DAC capacitor array of an LC-SAR combined DAC module for outputting thermometer codes DLCT <14:1>, the EN logic is connected with an enabling switch SW1 of the LC-SAR combined DAC module for outputting enabling signals EN, the input of the first comparator is connected with the output end of the LC-SAR combined DAC module for receiving output signals V M , and the or logic is connected with the SAR quantization loop module for outputting crossing signals TCROSS.
  6. 6. The LC-SAR combined DAC architecture with ARRM modules for use in LC ADCs of claim 5, wherein the SAR quantization loop module comprises a third comparator and a SAR logic; The output of the third comparator is connected with SAR logic and OR logic of the LC quantization loop module, the SAR logic is connected with a delay unit of the self-adaptive reset reference voltage source module ARRM and used for outputting a reset signal RST, the SAR logic is connected with a thermometer code binary code conversion circuit of the reset reference voltage source module ARRM and used for outputting a quantization completion signal CMPOK, and the SAR logic is also connected with an SAR DAC capacitor array of the LC-SAR combined DAC module and used for outputting binary codes DSAR <4:1>.
  7. 7. The method for operating the LC-SAR combined DAC structure with ARRM module applied to LC ADC is characterized by using the LC-SAR combined DAC structure with ARRM module applied to LC ADC according to claim 6, comprising the steps of: The tracking stage comprises the following steps of enabling a switch SW1 to be closed, enabling reset switches SW2 and SW3 to be opened, enabling thermometer codes DLCT <14:1> and binary codes DSAR <4:1> to keep an initial state, enabling an analog input signal V IN to be divided, enabling an output end to output an output signal V M in a 1:2 divided ratio with an input signal V IN , enabling an output signal V M to track the input signal V IN and enabling the output signal V to be between a high threshold voltage V H and a low threshold voltage V L threshold; In S2, in the LC coarse quantization stage, when the output signal V M is higher than the high threshold voltage V H or lower than the low threshold voltage V L , the enable switch SW1 is turned off, the reset switches SW2 and SW3 are turned off, the LC quantization loop module shifts the thermometer code DLCT (digital to analog) by 1 bit to the left or right to enable the lower polar plate of the LC DAC capacitor array to generate voltage jump, the output signal V M is overlapped with the voltage jump to finish coarse quantization, and the output signal V M is folded back between the high threshold voltage V H and the low threshold voltage V L after coarse quantization; S3, in a SAR fine quantization stage, an enabling switch SW1 is turned off, reset switches SW2 and SW3 are kept turned off, thermometer codes DLCT <14:1> are kept in a coarse quantization state, a SAR quantization loop module is started, a binary code DSAR <4:1> is changed for three times, a lower polar plate of a SAR DAC capacitor array generates three small-amplitude voltage jumps, an output signal V M is superimposed to finish fine quantization, residual voltage after LC quantization is compensated, and a quantization completion signal CMPOK and a reset signal RST are output after SAR quantization is finished; S4, in a reset stage, enabling a switch SW1 to be kept open, enabling reset switches SW2 and SW3 to be closed, enabling thermometer codes DLCT <14:1> and binary codes DSAR <4:1> to be reset to an initial state, enabling an output end output signal V M of an LC-SAR combined DAC to be reset to a common mode level V CM , and enabling an upper plate voltage of an input capacitor C IN to be reset to a V REF level output by an adaptive reset reference voltage source module ARRM; S5, in an input residual injection stage, after the reset of the output signal V M and the upper polar plate voltage of the input capacitor C IN is finished, the enabling switch SW1 is turned off, the reset switches SW2 and SW3 are turned off, thermometer codes DLCT <14:1> jump back to the quantized code value of LC, the lower polar plate of the LC DAC capacitor array generates a first voltage jump DeltaV 1, the output signal V M is overlapped with DeltaV 1 to generate a lower voltage jump, then the enabling switch SW1 is turned on again, the reset switches SW2 and SW3 are turned off, a second voltage jump DeltaV 2 is generated in the process of switching the upper polar plate voltage of the input capacitor C IN from the reference voltage V REF to the input signal V IN , the output signal V M is overlapped with 0.5XDeltaV 2 to generate an upper voltage jump, deltaV 1 and 0.5XDeltaV 2 are overlapped to form a voltage jump DeltaV=DeltaV ', deltaV' is the amplitude missing quantity of the input signal V IN during the period of turning off of the enabling switch SW1, and residual injection is realized; S6, circularly working, namely enabling a switch SW1 to be kept closed, resetting switches SW2 and SW3 to be kept open, enabling thermometer codes DLCT <14:1> to keep the quantized code value of LC, enabling binary codes DSAR <4:1> to keep an initial state, enabling an output signal V M to track an input signal V IN again, returning to the step S1 until the output signal V M exceeds a high threshold voltage V H and a low threshold voltage V L again, and repeating the steps S2-S5.
  8. 8. The method of claim 7, wherein the LC-SAR combined DAC architecture of the band ARRM module of the LC ADC is characterized in that the LC quantization loop module is entered when the output signal V M tracks the input signal V IN in proportion, the output signal V M voltage is compared with the common mode level V CM by a first comparator, the pull-up signal UD and the turn-over flag signal XD are generated by internal XD and UD logic, the turn-over flag signal XD is a flag when the pull-up signal UD turns over, the output signal V M is selected by a selector according to the pull-up signal UD, the other threshold voltage, i.e., the high threshold voltage V H or the low threshold voltage V L , the high threshold voltage V H or the low threshold voltage V L is compared by a second comparator to obtain a control signal XC when the high threshold voltage or the low threshold voltage V L is higher than or lower, the control signal XC is combined with the pull-up signal UD to be input to a shift register inside the LC quantization loop module, the thermometer code dl14:1 after the turn-over flag signal XD is processed, the turn-over flag signal XD and the control signal XC and the control signal is further processed to obtain the pass-through logic SAR logic loop module through the LC quantization loop module 76.
  9. 9. The method of claim 7, wherein the LC quantization loop module quantizes the residual voltage of V M , which is finely quantized when the crossing signal TCROSS is high, and the residual voltage of V M is compared with the V CM level four times by a third comparator and the result is input to the SAR logic to obtain a binary code DSAR <4:1> during the high level crossing signal TCROSS, and the quantized completion signal CMPOK and the reset signal RST are generated after the SAR quantization, and the two signals are input to the adaptive reset reference voltage source module ARRM to generate the corresponding reference voltage V REF in preparation for the subsequent reset and input residual injection.
  10. 10. The method according to claim 7, wherein in S5, the adaptive reset reference voltage source module ARRM generates the reference voltage V REF by using the quantized complete signal CMPOK as a control, the thermometer code binary code converting circuit converts the thermometer code DLCT <14:1> into the binary code DLCB <4:1>, the Delay unit delays the reset signal RST to obtain the RST_Delay signal, the binary codes DLCB <4:1> and the RST_Delay signal are input into the 4-16 decoder, the 4-16 decoder outputs signals to control the multiplexing switch, and the reference voltage V REF adapted to the binary code DLCB <4:1> is selected, so that DeltaV2=2× (DeltaV1+DeltaV').

Description

LC-SAR combined DAC structure with ARRM modules applied to LC ADC and working method thereof Technical Field The invention relates to the technical field of level cross-type ADC (analog to digital converter), in particular to an LC-SAR combined DAC structure with ARRM modules applied to an LC ADC and a working method thereof. Background The horizontal cross ADC (LevelCrossingADC, LC ADC for short) is a typical event-driven non-uniform sampling ADC, avoids ineffective sampling of the traditional uniform sampling ADC, reduces ineffective power consumption, and remarkably prolongs equipment endurance. Wherein the DAC in the LC ADC is the key module, the accuracy of the DAC determines the accuracy of the entire LC ADC. The DAC of the presently disclosed LC ADC is mainly of the following types: (1) A 1bit capacitive DAC, when the input signal crosses a threshold voltage 1LSB higher (or lower) than the common mode level (V CM), the reset switch is closed, resetting the output signal of the DAC back to the V CM common mode level. Such DACs have low power consumption, but because of the uncertainty of the quantization accuracy of the DACs due to the change of the slope of the input signal, the SNDR of the system is generally low, i.e. the effective bit ENOB of the ADC is low; (2) The binary capacitive DAC of Nbit divides the reference into N values by using a dichotomy, and the DAC output node is controlled by the code value of digital logic, which means that the voltage offset provided by the DAC is irrelevant to the input signal, the limitation of 1-bit DAC topology is overcome, the quantization precision is improved to a certain extent compared with the 1-bit capacitive DAC, the ideal requirement of high-precision application is not met, and the monotonicity is a problem; (3) The Nbit unitary DAC divides the reference into 2 N equal values (namely 2 N thermometer codes), the topological nature of the unitary DAC has monotonicity, the adaptability of the unitary DAC to the LC ADC is good, the quantization precision of the structural DAC is at the same level as that of the Nbit binary capacitive DAC, and although the precision is improved compared with that of a 1bit capacitive DAC, the application requirement of higher precision is still difficult to meet. Disclosure of Invention Accordingly, the invention aims to provide an LC-SAR combined DAC structure with ARRM module applied to an LC ADC and a working method thereof, which realizes coarse and fine two-stage quantization by fusing the LC DAC and the SAR DAC, and introduces an adaptive reset reference voltage source module to realize residual injection, thereby effectively compensating quantization error caused by loop delay without increasing system power consumption, reducing waveform distortion of signal reconstruction, and greatly improving the overall quantization accuracy of the LC ADC. The LC-SAR combined DAC structure comprises an LC-SAR combined DAC module, an LC quantization loop module, an SAR quantization loop module and an adaptive reset reference voltage source module ARRM, wherein the LC-SAR combined DAC module is connected with the LC quantization loop module and the SAR quantization loop module, the LC quantization loop module is connected with the SAR quantization loop module, and the adaptive reset reference voltage source module ARRM is connected with the LC-SAR combined DAC module, the LC quantization loop module and the SAR quantization loop module; The input end of the LC-SAR combined DAC module receives an analog input signal V IN, a reference voltage V REF, a common mode level V CM, a thermometer code DLCT <14:1>, a binary code DSAR <4:1>, an enable signal EN and a reset signal RST, and the output end of the LC-SAR combined DAC module transmits an output signal V M; The input end of the LC quantization loop module receives an output signal V M, a common mode level V CM, a high threshold voltage V H and a low threshold voltage V L, and the output end of the LC quantization loop module outputs a thermometer code DLCT <14:1>, a crossing signal TCROSS and an enable signal EN; The input end of the SAR quantization loop module receives an output signal V M, a common mode level V CM and a traversing signal TCROSS, and the output end of the SAR quantization loop module outputs a binary code DSAR <4:1>, a reset signal RST and a quantization completion signal CMPOK; The input of the adaptive reset reference voltage source module ARRM receives thermometer code DLCT <14:1>, reset signal RST, and quantization completion signal CMPOK, and the output of the adaptive reset reference voltage source module ARRM outputs reference voltage V REF. In a preferred embodiment, the circuit structure of the LC-SAR combined DAC module includes an input capacitor C IN, a SAR DAC capacitor array, an LC DAC capacitor array, and an output terminal, an upper plate of the input capacitor C IN is connected to an analog input signal V IN, a lower plate of the input capaci