CN-122026917-A - DAC resolution improving system and method based on time domain duty cycle synthesis

CN122026917ACN 122026917 ACN122026917 ACN 122026917ACN-122026917-A

Abstract

The invention discloses a DAC resolution improving system based on time domain duty cycle synthesis, which comprises a waveform input end, a duty cycle synthesis calculator, a low-order DAC, an analog low-pass filter and a waveform output end, wherein the waveform input end stores high-resolution ideal voltage signals required to be output by a user, the duty cycle synthesis calculator utilizes a time domain duty cycle synthesis strategy to carry out synthesis modulation on high-order deep target data, an output result of the duty cycle synthesis calculator is sent to the low-order DAC, a rear stage of the low-order DAC is connected with the waveform output end after being connected with the analog low-pass filter, the actual resolution of the DAC is improved by combining a low-order DAC and a duty cycle synthesis algorithm with the filter, resolution improvement can be realized on the basis of not changing an original DAC circuit, and a customizable bit number improvement selection is provided, so that the system is suitable for application in aspects such as piezoelectric driving control.

Inventors

LIU LU
MA DEMING
Mou Saijie
GU SHILIN
KONG MING
YU HANG
YU JING
JIANG HAOBIN

Assignees

中国计量大学
台州市黄岩区计量与产品质量安全检测研究院

Dates

Publication Date: 20260512
Application Date: 20251030

Claims (7)

1. A DAC resolution improving system based on time domain duty cycle synthesis is characterized by comprising a waveform input end, a duty cycle synthesis calculator, a low-order DAC, an analog low-pass filter and a waveform output end, wherein the waveform input end stores high-resolution ideal voltage signals required to be output by a user, the duty cycle synthesis calculator utilizes a time domain duty cycle synthesis strategy to conduct synthesis modulation on high-order deep target data, the output result of the duty cycle synthesis calculator is sent to the low-order DAC, and the low-order DAC is connected with the waveform output end after being connected with the analog low-pass filter.
2. The DAC resolution improving system based on time domain duty cycle synthesis according to claim 1, wherein the duty cycle synthesis calculator comprises a reading module, a cutting module, a calculating module, a time domain duty cycle synthesis module and a sending module, wherein the reading module is connected with a waveform input end, the cutting module is connected with the reading module, the sending module is connected with the low-level DAC interface, and the calculating module controls output time domain duty cycle synthesis parameter information to be connected with the cutting module and the sending module in a front-back mode.
3. The DAC resolution enhancement system according to claim 1, wherein the duty cycle synthesis calculator processes as follows: S1, a user inputs a high-resolution ideal voltage waveform data table to a reading module, and a certain voltage value is set as X; S2, intercepting a voltage value to be X 1 、X 2 by a interception module according to a required resolution value set by a user, wherein X 1 is a voltage bit value corresponding to the resolution of an original low-order DAC, and X 2 is a bit number corresponding to the resolution of the DAC to be lifted; Wherein, the , ; S3, directly sending the voltage bit value X 1 corresponding to the original low-order DAC resolution into an on-board DAC for output, and sending the bit number X 2 corresponding to the DAC resolution to be lifted into a calculation module for duty ratio calculation; s4, the calculation module circularly outputs a high-low level value X 1 +1、X 1 to the original low-level DAC through time-sharing calculation synthesis according to the number of bits to be lifted X 2 ; s5, the analog low-pass filter shapes the pulse waveform output by the low-order DAC and outputs the pulse waveform to the rear-stage driving output.
4. A DAC resolution enhancement system based on time domain duty cycle synthesis according to claim 3, wherein S4 is specifically: Mapping X 2 to a Threshold value in a time domain period, and assuming that the user-defined time domain period cycle number is N, calculating a modulation Threshold value Threshold by the following formula: ; by a counter frequency synchronized with the duty cycle The actual output is: 。
5. the DAC resolution improving method based on the time domain duty ratio synthesis is characterized by comprising the following steps of: 1) After the high-resolution waveform data is input into the system, the data is internally divided into two parts, namely an upper segment MSB and a lower segment LSB; The upper segment MSB is used for directly corresponding to the achievable bit width output of the original DAC; The LSB of the low-order segment is used for compensating the voltage variation which cannot be expressed by the original DAC resolution through modulation; 2) The proportional relation between the weight represented by the LSB of the low-order segment and the duty cycle is calculated and mapped into a determined duty cycle Threshold; 3) Comparing the increment value of the Duty-cycle frequency synchronous counter duty_CNT with the calculated Duty-cycle Threshold value; 4) When the increment value of the duty_CNT is smaller than the Duty ratio Threshold, the output value is increased by one stage in the current Duty ratio period, namely the upper segment MSB+1, otherwise, the upper segment MSB is maintained unchanged; 5) After the modulation process, the output resolution effect of the equivalent high-bit digital-to-analog converter is realized by combining the post low-pass filtering; theoretical prediction is performed by the following formula: the ideal output value is synthesized as follows in a time domain duty cycle: ; The simplification is as follows: ; and further, the effect of improving the output resolution of the digital-to-analog converter is realized, and the decimal part of the resolution is modulated and embedded in the time dimension according to a rule, so that the resolution is improved.
6. The DAC resolution enhancement method based on time-domain duty cycle synthesis according to claim 5, wherein in step 2), the value of the duty cycle Threshold parameter is constrained within the range of the duty cycle time counter to ensure the binarization of the modulation effect; ; ; wherein N is the user-defined time domain cycle number.
7. The DAC resolution enhancement method according to claim 5, wherein the Threshold is forcibly rounded for fractional jitter obtained by Threshold of time domain duty cycle, as follows: ideal output value , After rounding down to avoid jitter: 。

Description

DAC resolution improving system and method based on time domain duty cycle synthesis Technical Field The invention relates to the technical field of electronic circuits, in particular to a DAC resolution improvement method based on time domain duty cycle synthesis. Background In the operating scenario of a piezoceramic voltage controller, the controller needs to generate a stepped voltage signal with a specific level to drive a subsequent device, and in order to generate a voltage waveform signal with an adjustable frequency and voltage, an embedded device usually adopts a DAC chip controlled in a digital manner to generate high dynamic voltage output adjustment. In order to obtain the adjustable voltage signal with higher precision, a DAC chip with higher resolution is generally required, but in some high-precision projects, such as micro-nano scale piezoelectric positioning, the resolution of the DAC chip is often required to be difficult to reach by the existing industrial-scale DAC chip, the cost of the DAC with higher resolution is high, and the design on a hardware circuit often needs to put a lot of manpower and material resources. The mode of improving the resolution of the DAC can be divided into two modes of hardware design and software algorithm, and a cascade mode of synthesizing a high-order DAC by adopting a plurality of low-order DACs is generally adopted in the hardware design, so that the hardware cost is relatively high and the hardware is not easy to control. The existing algorithm resolution improvement technology is mainly based on a plurality of complicated numerical output calculations, is not easy to deploy on embedded equipment with relatively scarce hardware resources, has limited resolution improvement, and has the advantages that the output precision is greatly dependent on a waveform shaping circuit at a later stage, and the design is difficult. Thus, there is a strong need for a technique for achieving resolution improvement based on existing low-order DACs in combination with easy-to-calculate modulation algorithms without changing the original hardware circuitry. Disclosure of Invention The invention solves the problems of overcoming the defects of the prior art, and provides a DAC resolution improving method which is based on a low-order DAC and a time domain duty ratio synthesis technology and can realize the adjustable accuracy of output voltage waveform signals. The technical scheme of the invention is as follows: A DAC resolution improving system based on time domain duty cycle synthesis comprises a waveform input end, a duty cycle synthesis calculator, a low-order DAC, an analog low-pass filter and a waveform output end, wherein the waveform input end stores high-resolution ideal voltage signals required to be output by a user, the duty cycle synthesis calculator utilizes a time domain duty cycle synthesis strategy to carry out synthesis modulation on high-order deep target data, the output result of the duty cycle synthesis calculator is sent to the low-order DAC, and the rear stage of the low-order DAC is connected with the waveform output end after being connected with the analog low-pass filter. The duty ratio synthesis calculator comprises a reading module, a cutting module, a calculating module, a time domain duty ratio synthesis module and a sending module, wherein the reading module is connected with a waveform input end, the cutting module is connected with the reading module, the sending module is connected with the low-level DAC interface, and the calculating module controls output of time domain duty ratio synthesis parameter information and is connected with the cutting module and the sending module in a front-back mode. Further, the processing procedure of the duty ratio synthesis calculator is as follows: S1, a user inputs a high-resolution ideal voltage waveform data table to a reading module, and a certain voltage value is set as X; S2, intercepting a voltage value to be X 1、X2 by a interception module according to a required resolution value set by a user, wherein X 1 is a voltage bit value corresponding to the resolution of an original low-order DAC, and X 2 is a bit number corresponding to the resolution of the DAC to be lifted; Wherein, the ,; S3, directly sending the voltage bit value X 1 corresponding to the original low-order DAC resolution into an on-board DAC for output, and sending the bit number X 2 corresponding to the DAC resolution to be lifted into a calculation module for duty ratio calculation; s4, the calculation module circularly outputs a high-low level value X 1+1、X1 to the original low-level DAC through time-sharing calculation synthesis according to the number of bits to be lifted X 2; s5, the analog low-pass filter shapes the pulse waveform output by the low-order DAC and outputs the pulse waveform to the rear-stage driving output. Further, the S4 specifically is: Mapping X2 to a Threshold value in a time domain period, and assu