CN-122026918-A - Delta-sigma modulator with downsampled digital integrator

Abstract

Systems and methods for delta-sigma modulators with downsampled digital integrators. In various embodiments, a delta-sigma modulator may include a comparator configured to receive an analog input and provide a digital output at a sampling frequency, wherein the digital output is applied to an integrator path and a feed forward path, a digital integrator in the integrator path, wherein the digital integrator is configured to operate at a clock frequency less than the sampling frequency, and a summer configured to add an output of the integrator path to an output of the feed forward path to produce a bit stream.

Inventors

• Jan Daniel van der Kloster

Assignees

• 恩智浦有限公司

Dates

Publication Date

20260512

Application Date

20251111

Priority Date

20241111

Claims (10)

1. 1. A delta-sigma modulator, comprising: a comparator configured to receive an analog input and provide a digital output at a sampling frequency, wherein the digital output is applied to an integrator path and a feed forward path; a digital integrator in the integrator path, wherein the digital integrator is configured to operate at a clock frequency that is less than the sampling frequency, and A summer configured to add an output of the integrator path to an output of the feedforward path to produce a bit stream.
2. 2. The delta-sigma modulator of claim 1, further comprising a down sampler in the integrator path, wherein the down sampler is configured to provide a down sampled digital signal at the clock frequency to the digital integrator.
3. 3. A delta sigma modulator according to claim 1 additionally comprising an accumulator in said integrator path, wherein said accumulator is configured to receive said digital output and to provide a running sum of said digital output.
4. 4. A delta sigma modulator according to claim 3 wherein said accumulator comprises a Finite Impulse Response (FIR) filter.
5. 5. A delta sigma modulator according to claim 3 wherein said accumulator outputs an average of n values after receiving the nth value and wherein said digital amplifier is configured to divide said output by n.
6. 6. A delta sigma modulator according to claim 3 further comprising a digital amplifier coupled to said accumulator in said integrator path, wherein said digital amplifier is configured to normalize said running sum of said digital output and provide a running average of said digital output.
7. 7. The delta-sigma modulator of claim 6, further comprising a truncator coupled between the accumulator and the digital integrator, wherein the truncator is configured to reduce a bit width of an output of the accumulator.
8. 8. The delta-sigma modulator of claim 1, further comprising a truncator coupled between the digital integrator and the summer, wherein the truncator is configured to reduce a bit width of an output of the digital integrator.
9. 9. A delta-sigma modulator, comprising: A comparator configured to receive an analog input; An integrator path configured to receive a digital output of the comparator, wherein the integrator path comprises a digital integrator configured to operate at a clock frequency that is less than a sampling frequency of the comparator, and wherein the digital integrator adds a pole to a transfer function of the delta-sigma modulator, and A feed-forward path configured to receive the digital output of the comparator and to compensate for the pole.
10. 10. A method in an analog-to-digital converter (ADC), the method comprising: Generating a digital output using a comparator operating at a sampling frequency; providing the digital output to an integrating path and a feed-forward path; Downsampling data of the integration path to a frequency lower than the sampling frequency; Integrating the data of the integrating path with a digital integrator after the downsampling, and The integrated down-sampled data of the integration path is combined with the digital output to produce a bitstream.

Description

Delta-sigma modulator with downsampled digital integrator Technical Field The present disclosure relates generally to electronic circuits, and more particularly to delta-sigma modulators with downsampled digital integrators. Background Within a range of analog-to-digital converters (ADCs), there is a category that employs oversampling techniques to achieve high resolution digital outputs. Traditionally, in such ADCs, the analog/digital domain (e.g., quantizer) crossover and the digital/analog domain (e.g., feedback circuit) employ the same number of levels or bits, while the multi-level approach increases complexity. Alternatively, there are methods in which the number of quantizer levels is smaller than the feedback level, however, this has proven to be difficult to achieve due to stability problems. As the present inventors have recognized, ADCs with more feedback levels than quantization levels present challenges in maintaining stability, particularly when their digital components operate at the same clock frequency. Conventional solutions such as analog compensation or digital feedforward require a lot of hardware resources and result in increased noise. Disclosure of Invention In an illustrative, non-limiting embodiment, a delta-sigma modulator may include a comparator configured to receive an analog input and provide a digital output at a sampling frequency, wherein the digital output is applied to an integrator path and a feed forward path, a digital integrator in the integrator path, wherein the digital integrator is configured to operate at a clock frequency less than the sampling frequency, and a summer configured to add the output of the integrator path to the output of the feed forward path to produce a bit stream. The delta-sigma modulator may include a downsampler in the integrator path, wherein the downsampler is configured to provide the downsampled digital signal to the digital integrator at a clock frequency. Additionally or alternatively, the delta-sigma modulator may include an accumulator in the integrator path, wherein the accumulator is configured to receive the digital output and provide a running sum of the digital output. Additionally or alternatively, the delta-sigma modulator may include a digital amplifier in the integrator path, wherein the digital amplifier is configured to normalize a running average of the digital output of the accumulator. In some cases, the delta-sigma modulator may include an accumulator implemented as a FIR filter. The accumulator may output an average of the n values after receiving the n-th value, and the digital amplifier may be configured to divide the output by n. The delta-sigma modulator may include a truncator coupled between the accumulator and the digital integrator, wherein the truncator is configured to reduce a bit width of an output of the accumulator. Additionally or alternatively, the delta-sigma modulator may include a truncator coupled between the digital integrator and the summer, wherein the truncator is configured to reduce a bit width of an output of the digital integrator. The delta-sigma modulator may also include a digital amplifier in the feed-forward path. In operation, the integrator path may add a pole to the transfer function of the delta-sigma modulator, and the feed forward path may add a zero configured to compensate for the pole. Further, the comparator may be configured to receive an analog input via the loop filter. In another illustrative, non-limiting embodiment, a delta-sigma modulator may include a comparator configured to receive an analog input, an integrator path configured to receive a digital output of the comparator, wherein the integrator path includes a digital integrator configured to operate at a clock frequency that is less than a sampling frequency of the comparator, and wherein the digital integrator adds a pole to a transfer function of the delta-sigma modulator, and a feed forward path configured to receive the digital output of the comparator and compensate for the pole. The integrator path may include an accumulator configured to receive the digital signal and produce a running sum of the digital signal, followed by a normalizer configured to produce an average of the output of the accumulator. The integrator path may also include a downsampler configured to receive at least one of (a) a running average of the digital signal, or (b) a normalized running sum of the digital signal, and to provide the downsampled signal to the digital integrator. In another illustrative, non-limiting embodiment, in an ADC, a method may include generating a digital output using a comparator operating at a sampling frequency, providing the digital output to an integration path and a feed forward path, downsampling data of the integration path to a frequency lower than the sampling frequency, integrating the data of the integration path with a digital integrator after the downsampling, and combining the integrated downsa