CN-122026933-A - Millimeter wave broadband frequency agility receiving channel assembly

CN122026933ACN 122026933 ACN122026933 ACN 122026933ACN-122026933-A

Abstract

The application relates to the technical field of radio frequency and discloses a millimeter wave broadband agile frequency receiving channel component which comprises a duplex power dividing circuit, a self-checking coupling circuit, a receiving frequency synthesizer circuit and a power control circuit, wherein the duplex power dividing circuit is used for receiving a reference clock signal, outputting a first path of reference clock signal, a second path of reference clock signal and a third path of reference clock signal, the self-checking coupling circuit is used for receiving a radio frequency input signal and the second path of reference clock signal and generating a K frequency band radio frequency signal, the receiving frequency synthesizer circuit is used for receiving the third path of reference clock signal and outputting a local oscillator signal and a frequency synthesizer locking indication signal, the receiving frequency converting circuit is used for receiving the K frequency band radio frequency signal and the local oscillator signal to obtain a first intermediate frequency signal, the power control circuit is used for receiving the first path of reference clock signal to obtain a second intermediate frequency signal, and the reference detection signal is obtained. The application can realize wide radio frequency bandwidth, high spurious suppression, high frequency hopping speed, small frequency hopping step and support BIT self-checking function.

Inventors

YU KUAN
LI GUANG
ZHONG MINGHAI
WANG JING
CAI ZHE
XU ZHAOXU
TIAN SHUANG
Shi Fangjing
FAN MAOYU
QING JIE

Assignees

中国电子科技集团公司第十研究所

Dates

Publication Date: 20260512
Application Date: 20260413

Claims (10)

1. The millimeter wave broadband agile frequency receiving channel component is characterized by comprising a self-checking coupling circuit, a receiving frequency conversion circuit, a power control circuit, a duplex power dividing circuit, a reference detection circuit and a receiving frequency integrating circuit, wherein the self-checking coupling circuit, the receiving frequency conversion circuit, the power control circuit and the duplex power dividing circuit are sequentially connected; the double-station power division circuit is used for receiving a reference clock signal REF_IN and performing first processing on the reference clock signal REF_IN, and outputting a first path of reference clock signal REF1, a second path of reference clock signal REF2 and a third path of reference clock signal REF3; The self-checking coupling circuit is used for receiving a radio frequency input signal RF_IN and a second path of reference clock signal REF2, generating a K-band radio frequency signal RF1 and inputting the K-band radio frequency signal RF1 into the receiving frequency conversion circuit; The receiving frequency synthesizer circuit is used for receiving a third path of reference clock signal REF3, outputting a local oscillator signal LO and a frequency synthesizer locking indicating signal PLL_JC for outputting high and low levels externally in a DDS mixing and sectionalizing switch filtering mode, judging whether the receiving frequency synthesizer circuit works normally or not according to the frequency synthesizer locking indicating signal PLL_JC, and inputting the local oscillator signal LO into the receiving frequency conversion circuit; The receiving frequency conversion circuit is used for receiving a K-band radio frequency signal RF1 and a local oscillation signal LO, carrying out power distribution on the local oscillation signal LO to obtain two paths of local oscillation signals, carrying out second processing on one path of local oscillation signal to obtain a first signal, and carrying out third processing on the other path of local oscillation signal to obtain a second signal, carrying out fourth processing on the K-band radio frequency signal RF1 to obtain a third signal, carrying out frequency mixing on the first signal and the third signal, carrying out fifth processing on the mixed signals to obtain a fourth signal, carrying out frequency mixing on the second signal and the fourth signal to obtain a first intermediate frequency signal IF1, wherein the second processing comprises frequency multiplication, filtering and attenuation, the third processing comprises filtering, amplifying and attenuation, and the fourth processing comprises filtering, amplifying and attenuating; the power control circuit is used for receiving the first intermediate frequency signal IF1 and carrying out sixth processing on the first intermediate frequency signal IF1 to obtain a second intermediate frequency signal IF2 and inputting the second intermediate frequency signal IF2 into the duplex power division circuit; The reference detection circuit is used for receiving the first path of reference clock signal REF1 and performing seventh processing on the first path of reference clock signal REF1 to obtain a reference detection signal RFE_JC, and the reference detection signal RFE_JC is used for detecting whether the first path of reference clock signal REF1 is normal or not.
2. The millimeter wave wideband agile receive channel assembly of claim 1, wherein the duplex power splitting circuit is further configured to receive the second intermediate frequency signal IF2 and perform an eighth process on the second intermediate frequency signal if_out, the third intermediate frequency signal if_out being an output of the receive channel assembly, the eighth process comprising standing wave conditioning, filtering.
3. The millimeter wave wideband agile receive channel assembly of claim 1, wherein the self-test coupling circuit is to: IN a normal working mode, receiving a radio frequency input signal RF_IN, and directly outputting a K-frequency band radio frequency signal RF1; Receiving a second path of reference clock signal REF2 in a debugging self-checking mode, generating a K-band radio frequency self-checking signal RF_ZJ through phase locking, filtering and coupling to output a K-band radio frequency signal RF1, wherein the K-band radio frequency self-checking signal RF_ZJ is used for detecting whether the receiving channel component works normally or not, and after the radio frequency self-checking signal enters the receiving channel, if the receiving channel can normally output an intermediate frequency signal to the outside, the receiving channel works normally, otherwise, the receiving channel works abnormally; the K-band radio frequency signal RF1 is input into a receiving frequency conversion circuit.
4. The millimeter wave broadband agile frequency receiving channel assembly according to claim 1, wherein the self-checking coupling circuit comprises a phase locking unit, a control unit, a filtering unit and a radio frequency coupler, wherein the control unit is connected with the radio frequency coupler through the phase locking unit, the filtering unit and the radio frequency coupler in sequence; the FPGA of the control unit sends frequency control word information to the phase-locked unit to configure a register in the phase discriminator of the phase-locked unit; The phase-locked unit is used for receiving a second path of reference clock signal REF2, and a negative feedback loop is formed by a phase discriminator, a voltage-controlled oscillator and a loop filter in the phase-locked unit so as to realize frequency synthesis and output a K-frequency band radio frequency self-checking signal RF_ZJ; the filtering unit is used for filtering harmonic signals and spurious signals in the K-band radio frequency self-checking signal RF_ZJ; the radio frequency coupler is used for coupling the filtered signals output by the filtering unit, realizing self-checking signal coupling, and outputting K-frequency-band radio frequency signals RF1 to enter the receiving end frequency conversion circuit.
5. The millimeter wave broadband agile receiving channel assembly according to claim 1, wherein the duplex power dividing circuit comprises a first pi-type attenuator, a reference clock signal branch, an intermediate frequency signal branch and a reference branch, wherein the reference clock signal branch comprises a first inductor, a low-pass filter and a second pi-type attenuator which are sequentially connected; the intermediate frequency signal branch comprises a first capacitor C1, a high-pass filter and a third pi-type attenuator which are sequentially connected, wherein the second intermediate frequency signal passes through the intermediate frequency signal branch and the first pi-type attenuator and then externally outputs an intermediate frequency output signal IF_OUT; The input end of the power divider is connected with the output end of the second pi-type attenuator, and the output end is used for outputting a first path of reference clock signal REF1, a second path of reference clock signal REF2 and a third path of reference clock signal REF3.
6. The millimeter wave wideband agile receive channel assembly of claim 5, wherein said first pi type attenuator, said second pi type attenuator, and said third pi type attenuator are each configured to adjust the power of a reference clock signal and a second intermediate frequency signal IF2 and standing waves of input and output signals; the first inductor and the first capacitor C1 are used for adjusting phase matching between the reference clock signal and the second intermediate frequency signal so as to reduce transmission loss of the reference clock signal and the second intermediate frequency signal; the low pass filter is used for suppressing the out-of-band spurious of the reference clock signal and the high pass filter is used for suppressing the out-of-band spurious of the second intermediate frequency signal IF 2.
7. The millimeter wave wideband agile receiving channel assembly of claim 1, wherein the reference detection circuit comprises a fourth pi-shaped attenuator, a detection diode, and an FPGA chip connected in sequence; The fourth pi-shaped attenuator is used for performing power adjustment on the first path of reference clock signal REF1, obtaining a clock signal after power adjustment and inputting the clock signal into the detection diode; the detection diode is used for zero-biasing the clock signal after power adjustment to obtain detection voltage and inputting the detection voltage into the FPGA chip; The A/D circuit in the FPGA chip is used for sampling the detection voltage, outputting a LVTTL high-level reference detection signal RFE_JC if the level of the sampling signal is greater than or equal to a preset value, wherein the LVTTL high-level reference detection signal RFE_JC is used for indicating that a first path of reference clock signal REF1 is normal, and outputting a LVTTL low-level reference detection signal RFE_JC if the level of the sampling signal is less than the preset value, wherein the LVTTL low-level reference detection signal RFE_JC is used for indicating that the first path of reference clock signal REF1 is abnormal.
8. The millimeter wave wideband agile receive channel assembly of claim 1, wherein said receive frequency synthesis circuitry comprises an intermediate frequency branch, a local oscillator branch, a radio frequency branch, and a control circuit; the intermediate frequency branch circuit comprises a DDS, a pi-shaped attenuator and a band-pass filter which are sequentially connected; The local oscillation branch comprises a phase-locked loop (PLL) and a power divider which are connected in sequence; The radio frequency branch comprises a mixer, a switch filter bank, a numerical control attenuator and a temperature compensation attenuator which are connected in sequence; The control circuit comprises an FPGA, and the FPGA is used for configuring the DDS and the phase-locked loop (PLL); The FPGA configures the phase-locked loop PLL, the phase-locked loop PLL takes a third path of reference clock signal REF3 as a reference to generate local oscillation signals, the local oscillation signals are divided into two paths of output after passing through the power divider, one path of the local oscillation signals are input into the DDS and used as external clocks of the DDS, and the other path of local oscillation signals are used as local oscillation signals for receiving internal frequency mixing of the frequency synthesis circuit; The phase-locked loop PLL is configured to output a frequency-heddle-locking indication signal pll_jc, if the frequency-heddle-locking indication signal pll_jc is at a logic high level, the phase-locked loop PLL is indicated to work normally, and if the frequency-heddle-locking indication signal pll_jc is at a logic low level, the phase-locked loop PLL is indicated to work abnormally.
9. The millimeter wave wideband agile receive channel assembly of claim 1, wherein the receive frequency conversion circuitry comprises a radio frequency link, a two intermediate frequency link, a local oscillator link, and a two local oscillator link; the radio frequency link comprises a first band-pass filter, a first low-noise amplifier, a low-pass filter and a K-band mixer for realizing first-stage mixing, which are connected in sequence; The second intermediate frequency link comprises a first fixed attenuator, a second low noise amplifier, a second band-pass filter, a temperature compensation attenuator and a C-band mixer for realizing second-stage mixing, which are sequentially connected; The local oscillation link comprises a third fixed attenuator, a quadrupler, a fourth band-pass filter and a fourth fixed attenuator which are connected in sequence; the second local oscillator link comprises a third band-pass filter, a third low-noise amplifier and a second fixed attenuator which are sequentially connected; The input end of the power divider is used for receiving local oscillation signals LO, and the output end of the power divider is respectively connected with the input ends of the third fixed attenuator and the third band-pass filter; The method comprises the steps that a K-band radio frequency signal RF1 suppresses an image frequency interference signal through the first band-pass filter, reduces the noise coefficient of a receiving channel component through the first low-noise amplifier, suppresses a transmitting band spurious signal through the low-pass filter, and then enters a K-band mixer for realizing first-stage mixing to be mixed with a first local oscillator reference signal output by the local oscillator link, so that a mixed signal is obtained and is input into a first fixed attenuator of the two intermediate frequency links; The mixed signals sequentially pass through the first fixed attenuator and the second low noise amplifier to adjust the link level, then the combined spurious signals and the harmonic spurious signals of the two intermediate frequency links are filtered through the second band-pass filter, gain changes of a receiving channel component at different temperatures are compensated through the temperature compensation attenuator, and then the mixed signals enter a C-band mixer for realizing second-stage mixing and are mixed with a second local oscillator reference signal output by the two local oscillator links to obtain a first intermediate frequency signal IF1; The first local oscillation link and the second local oscillation link share the same local oscillation signal LO, the local oscillation signal LO outputs a quadruple frequency signal through the power divider, the quadruple frequency device and a fourth band-pass filter for inhibiting third harmonic and fifth harmonic, and the quadruple frequency signal outputs a first local oscillation reference signal after level adjustment through the fourth fixed attenuator; And the local oscillation signal LO passes through the power divider, the third band-pass filter, the third low-noise amplifier and the second fixed attenuator so as to carry out level adjustment on the local oscillation signal LO and output a second local oscillation reference signal.
10. The millimeter wave wideband agile receive channel assembly of claim 1, wherein the power control circuit comprises a first low pass filter, a fourth low noise amplifier, a digitally controlled attenuator, a sound meter filter, a fifth low noise amplifier, a fifth fixed attenuator, a second low pass filter connected in sequence; The first intermediate frequency signal IF1 is sequentially filtered by a first low-pass filter, amplified by a fourth low-noise amplifier, attenuated by a numerical control attenuator, filtered by a sound surface filter, amplified by a fifth low-noise amplifier, attenuated by a fifth fixed attenuator and filtered by a second low-pass filter, and then the second intermediate frequency signal IF2 is output.

Description

Millimeter wave broadband frequency agility receiving channel assembly Technical Field The application relates to the technical field of radio frequency, in particular to a millimeter wave broadband frequency agile receiving channel component. Background With the development of satellite communication technology, the satellite communication speed is continuously improved, and the millimeter wave frequency band is used as the main flow working frequency band of broadband satellite communication, so that the broadband satellite communication system has rich frequency spectrum resources, and has the advantages of supporting larger communication user access quantity, lower communication user access time delay, wider communication user use bandwidth and the like. However, since satellites are exposed to space, the orbit is fixed, and the satellites are more easily threatened by reconnaissance, interception, interference and the like from all directions, wei Tongtong communication systems generally use communication anti-interference technology based on broadband high-speed frequency hopping. The broadband frequency hopping technology makes the interference party difficult to predict the communication frequency through the pseudo-random hopping of the transmission carrier wave in a larger bandwidth along with time and the special long-period nonlinear design of the frequency hopping pattern of the receiving party and the transmitting party, and makes the tracking interference difficult to implement due to the restriction of factors such as short residence time of each hop and the like, and becomes the main technology of the anti-interference of the current satellite communication system. The satellite communication transceiver channel needs to support a larger channel bandwidth to meet the transmission capability of the communication system such as more user access, faster transmission rate, lower access delay and the like, and needs to support a faster frequency hopping rate to improve the anti-interference capability of the communication system. Therefore, the millimeter wave broadband anti-interference receiving channel with good technical performance index is designed, and has very key effect on improving the transmission performance and anti-interference performance of a satellite communication system. Disclosure of Invention Aiming at the problems of narrow working bandwidth, low frequency hopping speed, large frequency hopping step and the like of the traditional satellite communication receiving channel component, the application provides the millimeter wave broadband frequency agility receiving channel component which has the advantages of wide radio frequency bandwidth, high frequency hopping speed, small frequency hopping step, BIT self-checking support function and capability of improving the working bandwidth and the channel frequency hopping performance of a receiving channel. The application discloses a millimeter wave broadband frequency agility receiving channel component, which comprises a self-checking coupling circuit, a receiving frequency conversion circuit, a power control circuit, a duplex power dividing circuit, a reference detection circuit and a receiving frequency synthesizing circuit, wherein the self-checking coupling circuit, the receiving frequency conversion circuit, the power control circuit and the duplex power dividing circuit are sequentially connected; the double-station power division circuit is used for receiving a reference clock signal REF_IN and performing first processing on the reference clock signal REF_IN, and outputting a first path of reference clock signal REF1, a second path of reference clock signal REF2 and a third path of reference clock signal REF3; The self-checking coupling circuit is used for receiving a radio frequency input signal RF_IN and a second path of reference clock signal REF2, generating a K-band radio frequency signal RF1 and inputting the K-band radio frequency signal RF1 into the receiving frequency conversion circuit; The receiving frequency synthesizer circuit is used for receiving a third path of reference clock signal REF3, outputting a local oscillator signal LO and a frequency synthesizer locking indicating signal PLL_JC for outputting high and low levels externally in a DDS mixing and sectionalizing switch filtering mode, judging whether the receiving frequency synthesizer circuit works normally or not according to the frequency synthesizer locking indicating signal PLL_JC, and inputting the local oscillator signal LO into the receiving frequency conversion circuit; The receiving frequency conversion circuit is used for receiving a K-band radio frequency signal RF1 and a local oscillation signal LO, carrying out power distribution on the local oscillation signal LO to obtain two paths of local oscillation signals, carrying out second processing on one path of local oscillation signal to obtain a first signal, and carrying out third pro