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CN-122026942-A - FPGA capturing implementation method suitable for spread spectrum burst signals

CN122026942ACN 122026942 ACN122026942 ACN 122026942ACN-122026942-A

Abstract

The invention provides an FPGA capturing implementation method suitable for spread spectrum burst signals, which comprises the following steps of S1, carrying out matched filtering and downsampling processing on a received burst transmission sequence by a receiver to obtain a downsampled signal y (n), S2, carrying out secondary real-time sampling and storage on the sampled signal y (n), S3, carrying out real-time sampling and storage on pseudo codes, S4, carrying out coherent integration operation on sampling points and sampling pseudo code points, S5, designing parallelism of the coherent integration operation, S6, carrying out storage and FFT two-dimensional searching on a result of the coherent integration operation, and carrying out peak detection on a searching result, and S7, judging whether the capturing process is completed or not according to the result of the peak detection. The FPGA capturing implementation method suitable for the spread spectrum burst signal can shorten the synchronization time under a low-speed burst transmission system and improve the resource utilization rate.

Inventors

  • REN HUAN
  • ZHENG PENG
  • LI YAZE
  • MA RONG
  • LU JING

Assignees

  • 北京遥测技术研究所

Dates

Publication Date
20260512
Application Date
20251228

Claims (10)

  1. 1. The FPGA capturing implementation method suitable for the spread spectrum burst signal is characterized by comprising the following steps: s1, a receiver performs matched filtering and downsampling processing on a received burst transmission sequence to obtain a downsampled signal y (n); S2, carrying out secondary real-time sampling and storage on the sampling signal y (N), wherein the secondary sampling frequency f s is set to be f s =2×R s , the sampling time is 10ms, the total number of sampling points N s is N s =20×10 -3 ×R s , R s =b s ×N,R s is the pseudo code rate, b s is the symbol rate, N is the pseudo code length, a first memory is selected and all sampling points acquired within 20ms are stored by adopting a ping-pong buffer mechanism, the storage depth of the first memory is set to be L d =N s , the writing address update period of the first memory is 2/f s , and 2 sampling points are written in each time simultaneously; s3, sampling and storing the pseudo code in real time, wherein the sampling frequency of the pseudo code is set to be f c =f s , the length N of the pseudo code, the sampling frequency f c of the pseudo code is the inverse of half chip rate, 2X N sampling points can be obtained in a complete pseudo code period, the complete pseudo code sampling points are alternately stored by using a second memory and a third memory in a sampling time length of 20ms, the storage time units of the second memory and the third memory are 10ms, and the storage depth is set to be L c =2N; S4, performing coherent integration operation on the sampling points and the sampling pseudo code points, namely selecting coherent integration time T coh and incoherent integration number N nc , wherein the corresponding relation between different coherent integration times T coh and a frequency searching range f d is f d =1/T coh ; S5, designing the parallelism of coherent integration operation, wherein the parallelism N para of the correlator is set to be N para =2×N/(f clk /R s , and f clk =M×R s , M is the number of times that the second memory or the third memory can be completely and repeatedly read in 10 ms; s6, storing a result of the coherent integration operation, performing FFT two-dimensional search, and performing peak detection on the search result; And S7, judging whether the capturing process is finished or not according to the peak value detection result.
  2. 2. The method of claim 1, wherein in step S1, the burst transmission sequence comprises a pilot frequency part and a data part, wherein the pilot frequency part has a length of K p , the pilot frequency content is a fixed 0/1 sequence and has good autocorrelation property, the data part has a length of K d , the data content is a random 0/1 sequence, the FPGA operates as a master clock f clk , the symbol rate is b s , the pseudo code length is N, the pseudo code rate is R s =b s ×N, and the Doppler range required to be captured by the index is-f d /2~f d /2.
  3. 3. The method for capturing an FPGA of a spread spectrum burst signal according to claim 2, wherein the method for downsampling in step S1 is that an original zero intermediate frequency signal x (n) is downsampled by K times to obtain the downsampled signal y (n), and a sampling rate f dclk =f clk /K and f dclk ≥2×R s of the downsampled signal y (n), where f clk is a sampling rate of the original zero intermediate frequency signal x (n), K is a downsampling factor, and K is a positive integer.
  4. 4. The method for capturing FPGA of spread spectrum burst signals as set forth in claim 1, wherein the method for alternately storing in step S3 is that any single port of the second memory is enabled to store pseudo codes for 10ms, and any single port of the second memory is enabled to store pseudo codes for 10ms, wherein an update period of a single port memory address is T c =1/f c , each address writes 2 pseudo code sampling points, sampling point intervals of single address storage are half chips, and sampling point intervals of adjacent address storage are half chips.
  5. 5. The method for capturing FPGA of spread spectrum burst signals as recited in claim 4, wherein each single-port memory address stores two adjacent sampling points when storing original sampling points, and the stored sampling points are not repeated.
  6. 6. The FPGA capture implementation method for spread spectrum burst signals, which is characterized by comprising the following steps of simultaneously reading sampling data and pseudo codes from a first memory and a second memory respectively in an FPGA working main clock f clk Lower part(s) , for coherent operation, wherein 2 XN times of sampling data are read in a 10ms mode, each time of reading sampling data is y 0 、y 1 、y 2 ……y Ns-1 , 2 XN times of pseudo code data are read in a 10ms mode, two ports of the second memory can simultaneously read pseudo codes, two address interfaces of the first memory or the second memory respectively read first addresses and second addresses, the reading address update periods of any single port of the first memory and the second memory are all whole chips, each time of starting to execute a reading operation, the first time of starting to execute a reading operation of pseudo code input 0 and pseudo code input 1 are sequentially generated by a shifting operation of the pseudo code input 0 and the pseudo code input 1, each time of completing 10ms data sampling operation starts to perform coherent integration operation, the first time of reading data from the first memory or the second memory respectively reads the pseudo codes and the sampling data from the first memory and the pseudo codes are sampled and the sampling operation of the pseudo codes is performed one by one time.
  7. 7. The method for implementing FPGA acquisition of spread spectrum burst signal as recited in claim 6, wherein step S6 further comprises the steps of: S61, sequentially storing the accumulated results of the selective coherent integration operation into a fourth memory and a fifth memory, wherein different rows of the fourth memory respectively correspond to coherent results of the same group of sampling data and different groups of pseudo codes, and the fifth memory continues to store when the fourth memory is fully written; S62, carrying out parallel correlation calculation on stored sampling data and pseudo code data according to the parallelism design, and carrying out FFT two-dimensional search after carrying out accumulation operation on N coh =T coh ×R s correlation results; S63, carrying out parallel frequency search on Doppler frequency shift and code phase of the signal by adopting a linear search method after FFT processing, wherein the two-dimensional search times are 2 multiplied by N, and spreading peak detection after each FFT is completed.
  8. 8. The method of claim 7, wherein in step S63, the position indexes of the detected peak values correspond to a frequency parameter max f and a code phase parameter max c, the FFT resolution Δf is Δf=f d /N fft , the code phase accuracy Δd is Δd=1/2, the detected peak values are converted into final estimated frequency offset f cap as f cap =max f×Δf, the code offset Ccap as Ccap =max c×Δd, and N fft is the number of FFT points selected.
  9. 9. The method for implementing FPGA capture of spread spectrum burst signal as set forth in claim 1, wherein the method for determining the peak detection result in step S7 is characterized by comparing the detected maximum peak value with a preset capture threshold, and if the detected maximum peak value exceeds the capture threshold, determining that capture is successful, and completing carrier synchronization and pseudo code synchronization, wherein the capture threshold is set as a noise power value.
  10. 10. The method for capturing FPGA of spread spectrum burst signals according to any one of claims 1 to 9, further comprising the steps of: And S8, repeating the steps S6-S7 until the maximum peak value exceeds the capture threshold value for three times to judge that the capture is successful.

Description

FPGA capturing implementation method suitable for spread spectrum burst signals Technical Field The invention relates to the technical field of satellite communication, in particular to an FPGA capturing implementation method suitable for spread spectrum burst signals. Background The FPGA is a product developed based on Programmable Array Logic (PAL), general array logic (EPLD) and other devices, and is an editable logic chip capable of completing general functions, i.e., a function of programming the editable logic chip to realize certain logic processing. The FPGA has high integration level and stronger logic function, so that the FPGA has higher flexibility and is widely applied to the technical fields of communication, electronics, time-frequency signal processing, aerospace and the like. However, under the high-speed clock, the FPGA has the problem of insufficient resources or excessive occupation when capturing low-speed signals. The publication number CN118249973A discloses a method, a device and a computing device for timing synchronization in a digital communication system, and a method for increasing the accuracy of a synchronous position by adopting a secondary verification method. This is a timing synchronization method that increases the acquisition probability by increasing the number of authentications. The method has higher requirements on the signal transmission system, can not meet the rapid acquisition and tracking requirements of the short pilot burst signal sequence, needs a fixed pilot symbol with enough length for the segmentation and differential accumulation calculation of the received signal, and has insufficient signal sequence length of the burst transmission system to support the secondary verification operation. The publication number CN117615047A discloses a design method of a Beidou short message receiver based on an FPGA, which is characterized in that a short message sampling data buffer zone module is combined with a capturing module, and two paths of capturing parallel time sequence control are designed to realize the synchronization process of frame heads. The method requires time for the stability of the loop tracking module, and is not suitable for capturing and tracking burst signals. Disclosure of Invention The invention provides a method for realizing FPGA capturing of spread spectrum burst signals, which aims to solve the technical problems of insufficient resources or excessive occupation when the FPGA captures the low-speed signals under a high-speed clock in the prior art, and can shorten the synchronization time under a low-speed burst transmission system and improve the utilization rate of resources. The invention provides an FPGA capturing implementation method suitable for spread spectrum burst signals, which comprises the following steps: s1, a receiver performs matched filtering and downsampling processing on a received burst transmission sequence to obtain a downsampled signal y (n); S2, sampling and storing a sampling signal y (N) in a secondary real-time mode, wherein the secondary sampling frequency f s is set to be f s=2×Rs, the sampling time is 10ms, the total number of sampling points N s is N s=20×10-3×Rs, R s=bs×N,Rs is pseudo code rate, b s is symbol rate, N is pseudo code length, a first memory is selected and all sampling points acquired within 20ms are stored by adopting a ping-pong buffer mechanism, the storage depth of the first memory is set to be L d=Ns, the writing address updating period of the first memory is 2/f s, and 2 sampling points are written in each time simultaneously; S3, sampling and storing the pseudo code in real time, wherein the sampling frequency of the pseudo code is set to be f c=fs, the length N of the pseudo code, the sampling frequency f c of the pseudo code is the inverse of half chip rate, 2X N sampling points can be obtained in a complete pseudo code period, the complete pseudo code sampling points are alternately stored by using a second memory and a third memory in a sampling time length of 20ms, the storage time units of the second memory and the third memory are 10ms, and the storage depth is set to be L c =2N; S4, carrying out coherent integration operation on the sampling points and the sampling pseudo code points, namely selecting coherent integration time T coh and incoherent integration number N nc, wherein the corresponding relation between different coherent integration times T coh and a frequency searching range f d is f d=1/Tcoh; S5, designing the parallelism of coherent integration operation, namely setting the parallelism N para of a correlator as N para=2×N/(fclk/Rs), wherein f clk=M×Rs, M is the number of times that the second memory or the third memory can be read repeatedly in a complete way within 10ms, and because the original sampling data in the first memory can be read repeatedly in M times within 10ms, wherein M=f clk/Rs, and the correlation operation of all stored original sampling data