CN-122026991-A - High-speed data transmission demodulation device based on multi-GPU parallel processing

Abstract

The invention discloses a high-speed data transmission demodulation device based on multi-GPU parallel processing, and belongs to the technical field of satellite-ground data transmission. The device comprises a digital down-conversion unit, a low-pass filtering unit, a half-band filter bank unit, a digital resampling unit, a complex filtering unit, a digital AGC unit, a data extraction unit, a carrier Doppler frequency offset estimation unit, a forming coefficient storage unit, a coefficient convolution unit, a coefficient interception unit, a control word scanning unit, a carrier phase error compensation unit, a timing error calculation unit, a carrier phase error calculation unit, an error accumulation unit and an error weighting unit. The invention has the characteristics of high implementation reliability, high stability, low implementation complexity and the like.

Inventors

• LI CHAO
• Xing Cuiliu
• ZHANG YANAN
• LI JICHANG
• CHENG YAYONG
• ZHAO XIANMING
• WANG XINKUO

Assignees

• 中国电子科技集团公司第五十四研究所

Dates

Publication Date

20260512

Application Date

20260130

Claims (2)

1. 1. The high-speed data transmission demodulation device based on multi-GPU parallel processing is characterized by comprising a digital down-conversion unit (1), a low-pass filtering unit (2), a half-band filter bank unit (3), a first digital resampling unit (4-1), a second digital resampling unit (4-2), a first complex filtering unit (5-1), a second complex filtering unit (5-2), a digital AGC unit (6), a data extraction unit (7), a carrier Doppler frequency offset estimation unit (8), a forming coefficient storage unit (9), a coefficient convolution unit (10), a coefficient interception unit (11), a first control word scanning unit (12-1), a second control word scanning unit (12-2), a carrier phase error compensation unit (13), a timing error calculation unit (14), a carrier phase error calculation unit (15), a first error accumulation unit (16-1), a second error accumulation unit (16-2), a first error weighting unit (17-1) and a second error weighting unit (17-2).
2. 2. The high-speed data transmission demodulation device based on multi-GPU parallel processing according to claim 1, wherein the digital down-conversion unit (1) performs digital down-conversion processing on a middle-frequency sampling signal, and utilizes an input carrier Doppler frequency offset estimation signal to complete carrier coarse synchronization of the signal, and simultaneously generates and outputs two paths of I/Q quadrature baseband signals; the low-pass filtering unit (2) processes the I/Q two-way quadrature baseband signals output by the digital down-conversion unit (1) and then transmits the signals to the half-band filter bank unit (3); The half-band filter group unit (3) performs half-band filtering processing of different combinations on different symbol rate signals by using the input symbol rate setting value, and transmits the processed signals to the first digital resampling unit (4-1); the first digital resampling unit (4-1) performs digital resampling processing on the input I/Q two-way quadrature baseband signals by using the input symbol rate setting value, generates 2 times of sampled I/Q two-way quadrature baseband signals and outputs the 2 times of sampled I/Q two-way quadrature baseband signals; The first complex filtering unit (5-1) receives I/Q two-way quadrature baseband output by the first digital resampling unit (4-1), carries out matched filtering and pre-equalization processing on input I/Q quadrature baseband signals according to the real part and the imaginary part coefficients of the filter transmitted by the coefficient intercepting unit (11), and transmits the processed I/Q quadrature baseband signals to the digital AGC unit (6), wherein complex filtering coefficients used by the first complex filtering unit (5-1) are generated by the forming coefficient storage unit (9), the coefficient convolution unit (10) and the coefficient intercepting unit (11); A shaping coefficient storage unit (9) selects a shaping coefficient currently used from a pre-stored shaping coefficient set according to shaping coefficient setting parameters, and transmits the shaping coefficient to a coefficient convolution unit (10); The coefficient convolution unit (10) carries out complex convolution operation on the real part and the imaginary part of the input pre-equalization coefficient and the currently input forming coefficient, and transmits the coefficient obtained by operation to the coefficient interception unit (11); The coefficient clipping unit (11) clips the input filter coefficient according to the filter order set by the first complex filtering unit (5-1), and transmits the clipped coefficient to the first complex filtering unit (5-1); The digital AGC unit (6) detects the power of two paths of peak point signals of the I/Q in the input signal, adjusts the power of the input signal according to the detection value and outputs the adjusted power; the I/Q quadrature baseband signals output by the digital AGC unit (6) are split to generate two groups of signals, wherein the first group of I/Q quadrature baseband signals are transmitted to the data extraction unit (7), and the second group of I/Q quadrature baseband signals are transmitted to the second digital resampling unit (4-2); The data extraction unit (7) extracts peak points of the input signals and transmits the extracted peak points to the carrier Doppler frequency offset estimation unit (8); The carrier Doppler frequency offset estimation unit (8) carries out carrier Doppler frequency offset estimation on the input I/Q quadrature baseband signal according to the input modulation system setting parameters and the symbol rate setting parameters, and transmits the frequency offset estimation value to the digital down-conversion unit (1); the second digital resampling unit (4-2) carries out digital resampling processing on the input I/Q quadrature baseband signal according to the control word sweep setting value output by the control word sweep unit (12-1) and the timing error output by the first error weighting unit (17-1) to complete the timing synchronization of the input signal, and transmits the signal after the timing synchronization to the carrier phase error compensation unit (13); The carrier phase error compensation unit (13) carries out carrier phase error compensation processing on the input I/Q quadrature baseband signals according to the control word sweep setting value output by the control word sweep unit (12-2) and the carrier phase error output by the second error weighting unit (17-2) to complete carrier synchronization of the input signals and output the signals after the carrier synchronization, the I/Q quadrature baseband signals output by the carrier phase error compensation unit (13) are split to generate three groups of I/Q quadrature baseband signals, wherein the first group of I/Q quadrature baseband signals are transmitted to the timing error extraction unit (14), the second group of I/Q quadrature baseband signals are transmitted to the carrier phase error extraction unit (15), and the third group of I/Q quadrature baseband signals are transmitted to the second complex filtering unit (5-2); A timing error extraction unit (14) processes the input signal, generates a timing error, and transmits the timing error to a first error accumulation unit (16-1); A first error accumulation unit (16-1) performs accumulation processing on the input timing error according to an internal timer, and transmits the accumulated timing error signal to a first error weighting unit (17-1); A first error weighting unit (17-1) performs weighting processing on the input timing error accumulation value according to the symbol rate setting parameter, and transmits the timing error after the weighting processing to a second digital resampling unit (4-2), wherein the weighting coefficient of the weighting processing is in a proportional relation with the inverse symbol rate; A carrier phase error extraction unit (15) processes the input signal, generates a carrier phase error, and transmits the carrier phase error to a second error accumulation unit (16-2); A second error accumulation unit (16-2) performs accumulation processing on the input carrier phase error according to an internal timer, and transmits the accumulated carrier phase error signal to a second error weighting unit (17-2); a second error weighting unit (17-2) performs weighting processing on the input carrier phase error accumulation value according to the symbol rate setting parameter, and transmits the carrier phase error after the weighting processing to a carrier phase error compensation unit (13), wherein the weighting coefficient of the weighting processing is in a proportional relation with the inverse symbol rate; the second complex filter unit (5-2) equalizes the input I/Q signal according to the input real part of the equalization coefficient and the imaginary part of the equalization coefficient, and outputs the equalized signal.

Description

High-speed data transmission demodulation device based on multi-GPU parallel processing Technical Field The invention relates to the technical field of satellite-ground data transmission, in particular to a high-speed data transmission demodulation device based on multi-GPU parallel processing, which is suitable for receiving and demodulating high-speed data transmission signals in a satellite data ground receiving station data receiving subsystem. Background In the current satellite-ground data transmission system, a high-speed data transmission demodulator mainly adopts two implementation structures of baseband sampling and intermediate frequency sampling. For baseband sampling, an analog quadrature down-conversion component is typically used to convert the intermediate frequency analog signal to an analog quadrature baseband signal, which is then sampled and subsequently processed. However, as the bandwidth of the high-speed data signal increases gradually, the high-order modulation system is gradually applied, so that the non-ideal characteristics of the analog devices and the differences among the devices can have an increasing effect on the signal reception, and the reception performance of the device is reduced, which results in complex hardware design and difficult debugging of the device. For intermediate frequency sampling, the traditional high-speed data transmission baseband is realized by adopting FPGA hardware, and the device can efficiently complete demodulation of high-speed data transmission signals through the signal processing process of an FPGA pipeline. However, the FPGA has higher hardware cost when designing and implementing, and in the design process, the timing constraint and the cross-clock domain interaction of the algorithm implementation need to be additionally considered. Meanwhile, because the FPGA pin definition and the chip model selection are different, the program cannot be directly operated in different hardware platforms through simple debugging, so that the debugging process of the demodulation device is complex, and the development difficulty is high. Some traditional demodulation devices are also realized by using a GPU, but the device can process a smaller signal bandwidth or cannot process a high-order modulation system. Disclosure of Invention The invention aims to avoid the defects in the background art and provide a high-speed data transmission demodulation device based on multi-GPU parallel processing. The invention has the characteristics of high implementation reliability, high stability, low implementation complexity and the like. The purpose of the invention is realized in the following way: a high-speed data transmission demodulation device based on multi-GPU parallel processing comprises a digital down-conversion unit 1, a low-pass filtering unit 2, a half-band filter bank unit 3, a first digital resampling unit 4-1, a second digital resampling unit 4-2, a first complex filtering unit 5-1, a second complex filtering unit 5-2, a digital AGC unit 6, a data extraction unit 7, a carrier Doppler frequency offset estimation unit 8, a forming coefficient storage unit 9, a coefficient convolution unit 10, a coefficient interception unit 11, a first control word scanning unit 12-1, a second control word scanning unit 12-2, a carrier phase error compensation unit 13, a timing error calculation unit 14, a carrier phase error calculation unit 15, a first error accumulation unit 16-1, a second error accumulation unit 16-2, a first error weighting unit 17-1 and a second error weighting unit 17-2. Further, the digital down-conversion unit 1 performs digital down-conversion processing on the intermediate frequency sampling signal, and utilizes the input carrier Doppler frequency offset estimation signal to complete carrier coarse synchronization of the signal, and simultaneously generates and outputs two paths of I/Q quadrature baseband signals; the low-pass filtering unit 2 processes the I/Q two-way quadrature baseband signals output by the digital down-conversion unit 1 and then transmits the signals to the half-band filter bank unit 3; the half-band filter group unit 3 performs half-band filtering processing of different combinations on different symbol rate signals by using the input symbol rate setting value, and transmits the processed signals to the first digital resampling unit 4-1; The first digital resampling unit 4-1 performs digital resampling processing on the input I/Q two-way quadrature baseband signals by using the input symbol rate setting value, generates 2 times of sampled I/Q two-way quadrature baseband signals and outputs the 2 times of sampled I/Q two-way quadrature baseband signals; The first complex filtering unit 5-1 receives the I/Q two-way quadrature baseband output by the first digital resampling unit 4-1, carries out matched filtering and pre-equalization processing on the input I/Q quadrature baseband signal according to the real part of the