CN-122026995-A - Double-interface satellite-borne signal receiving and transmitting system

CN122026995ACN 122026995 ACN122026995 ACN 122026995ACN-122026995-A

Abstract

The invention provides a dual-interface satellite-borne signal receiving and transmitting system, which at least comprises two groups of mutually independent and redundantly configured signal receiving and transmitting channels, wherein any signal receiving and transmitting channel comprises a receiving and transmitting interface chip assembly, an external interface, a peripheral configurable circuit and a controller, wherein the receiving and transmitting interface chip assembly is used for realizing the transmission and/or the reception of differential signals, the external interface is used for being electrically connected with a differential connector outside a satellite-borne device, the peripheral configurable circuit is respectively electrically connected with the receiving and transmitting interface chip assembly and the external interface, the peripheral configurable circuit is used for carrying out coupling, impedance matching, amplitude limiting protection and/or fault isolation on the signal receiving and transmitting channels based on different configuration conditions, and the controller is electrically connected with the receiving and transmitting interface chip assembly through the peripheral configurable circuit and is used for enabling the acquisition processing or the transmission processing of differential data. The invention realizes double-interface compatibility, double-channel redundancy, configurable reconstruction of peripheral network and adaptation to satellite-borne signal receiving and transmitting systems with various external wiring modes on the same hardware platform.

Inventors

PU JIANFU
ZHANG GUODONG
ZHU DI
LIU YIFENG
CHEN BIWEN

Assignees

上海航天测控通信研究所

Dates

Publication Date: 20260512
Application Date: 20260213

Claims (10)

1. The double-interface satellite-borne signal receiving and transmitting system is characterized by at least comprising two groups of mutually independent and redundantly configured signal receiving and transmitting channels, and any signal receiving and transmitting channel comprises: The receiving-transmitting interface chip assembly is used for realizing the transmission and/or the reception of differential signals; the external interface is used for being electrically connected with a differential connector outside the satellite-borne equipment; the peripheral configurable circuit is respectively and electrically connected with the receiving-transmitting interface chip assembly and the external interface and is used for carrying out coupling, impedance matching, amplitude limiting protection and/or fault isolation on the signal receiving-transmitting channel based on different configuration conditions; And the controller is electrically connected with the transceiver interface chip assembly through the peripheral configurable circuit and is used for enabling acquisition processing or transmission processing of differential data.
2. The dual-interface star-signal transceiver system of claim 1, wherein the transceiver interface chips in the transceiver interface chip assembly are selectively configurable as LVDS transceiver interface chips or RS422 transceiver interface chips with the same supply voltage, compatible packaging, and different pins; The receiving and transmitting interface chip component reserves a shared packaging bonding pad for installing the LVDS receiving and transmitting interface chip and the RS422 receiving and transmitting interface chip on the same printed board of the satellite-borne signal receiving and transmitting system; The transceiver interface chip assembly is configured to selectively load and unload the LVDS transceiver interface chip and the RS422 transceiver interface chip to switch LVDS interface and RS422 interface functions of the satellite-borne signal transceiver system.
3. The dual-interface star signal transceiver system of claim 2, wherein the packaging of said LVDS transceiver interface chip and said RS422 transceiver interface chip comprises forward molding and reverse molding to form a clockwise and counterclockwise pin sequence; The printed board is configured such that the front side thereof is mounted with the transceiver interface chip of the front molding package and the back side thereof is mounted with the transceiver interface chip of the back molding package.
4. The dual-interface on-board signal transceiver system of claim 1, wherein the peripheral configurable circuit comprises a first circuit unit and a second circuit unit; The first circuit unit comprises a first component, a second resistor, a third resistor, a fourth resistor, a fifth resistor and a diode which are selectively assembled, wherein the first component comprises a first resistor or a capacitor; The first end of the first component is electrically connected with a second port of the transceiver interface chip, the second end of the first component is electrically connected with the first end of the fifth resistor, the second end of the fifth resistor is electrically connected with the first port of the second circuit unit, the first end of the third resistor is electrically connected with a common node of the first component and the fifth resistor, the second end of the third resistor is electrically connected with a cathode of the diode, an anode of the diode is connected with a power supply, the first end of the second resistor is electrically connected with a common node of the fifth resistor and the second circuit unit, the second end of the second resistor is electrically connected with a grounding end, the first end of the fourth resistor is electrically connected with a fourth port of the second circuit unit, and the second end of the fourth resistor is electrically connected with the grounding end; The first group of ports of the external interface are electrically connected with the common node of the first component and the fifth resistor, and the second group of ports of the external interface are electrically connected with the common node of the fifth resistor and the second circuit unit; the second port of the second circuit unit is electrically connected with the first port of the transceiver interface chip, the third port of the second circuit unit is electrically connected with the third port of the transceiver interface chip, and the fourth port of the second circuit unit is electrically connected with the controller; the second circuit unit comprises two groups of resistors, capacitors and/or inductors, wherein two ends of the two groups of resistors, capacitors and/or inductors are respectively configured as a first port and a second port of the second circuit unit and a third port and a fourth port of the second circuit unit, or two ends of the two groups of resistors, capacitors and/or inductors are respectively configured as a first port and a third port of the second circuit unit and a second port and a fourth port of the second circuit unit.
5. The dual-interface on-board signal transceiving system of claim 4, wherein said first circuit unit and said second circuit unit of two sets of said signal transceiving channels are device-selectively installed or uninstalled to switch between a back-up mode and a non-back-up mode of the on-board signal transceiving system; in the backup mode, two groups of signal receiving and transmitting channels are installed at the same time and are connected with the external interface together, and in the non-backup mode, only any group of signal receiving and transmitting channels are installed and connected with the external interface.
6. The dual-interface on-board signal transceiving system of claim 4, wherein when said transceiver interface chip components of both sets of said signal transceiver channels are each configured as LVDS inputs, said peripheral configurable circuitry is configured as a combination of DC or AC coupling, backup or not, set bias circuitry, or not set bias circuitry; when the transceiver interface chip assemblies of the two groups of signal transceiver channels are configured as LVDS outputs, the peripheral configurable circuit is configured as a combination of DC coupling or AC coupling, backup or non-backup; When the transceiver interface chip assemblies of both sets of the signal transceiver channels are configured as RS422 inputs, the peripheral configurable circuitry is configured as a combination of low power mode or non-low power mode, back-up or not, set bias circuitry or not; the peripheral configurable circuitry is configured to be backed up or not backed up when the transceiver interface chip components of both sets of the signal transceiver channels are configured as RS422 outputs.
7. The dual-interface on-board signal transceiving system of claim 4, wherein when said transceiver interface chip components of both sets of said signal transceiver channels are configured as inputs and outputs of RS422, respectively, said peripheral configurable circuitry is configured as a combination of a low power mode or a non-low power mode, with or without bias circuitry; When the transceiver interface chip assemblies of the two sets of the signal transceiver channels are respectively configured as input and output of LVDS, the peripheral configurable circuit is configured as a combination of dc coupling or ac coupling, setting a bias circuit or not setting a bias circuit.
8. The dual-interface satellite-borne signal receiving and transmitting system according to claim 4, wherein a fly-line connection mode is adopted between the external interface and the differential connector; when the external interface and the differential connector are connected by adopting an RS422 differential circuit double-point double-line, the two groups of flying wires are respectively configured to be correspondingly connected to an odd-number pin and an even-number pin of the external interface from the differential connector.
9. The dual-interface on-board signal transceiver system of claim 4, wherein the peripheral configurable circuit is configured as a low level input when no transceiver interface chip is mounted in the transceiver interface chip assembly.
10. The dual-interface on-board signal transceiver system of claim 4, wherein the I/O pin direction of the controller is configurable to be input or output to match an input or output configuration of a transceiver interface chip of the transceiver interface chip assembly; The controller includes an FPGA.

Description

Double-interface satellite-borne signal receiving and transmitting system Technical Field The invention belongs to the technical field of data transceiving, and particularly relates to a dual-interface satellite-borne signal transceiving system. Background LVDS (Low Voltage DIFFERENTIAL SIGNALING) interface and RS422 (TIA/EIA-422) interface are widely used for data transmission in satellite-borne electronic equipment due to their good anti-interference capability and strong common mode rejection capability. In engineering application, the existing satellite-borne product is often configured with different numbers of LVDS or RS422 transceiving channels according to specific task requirements, and different types of equipment have differences in interface types, channel numbers, input/output directions, redundancy backup modes and the like. For example, for differential signal input applications, different devices may respectively use a dc coupling or ac coupling mode, and choose whether to set a bias circuit according to anti-noise requirements, for differential signal output applications, termination modes, isolation modes, and driving modes of different devices may also be different, and in addition, in order to meet reliability requirements in a satellite-borne system, an a/B redundancy backup is often used for an interface channel, but the backup mode, wiring mode, and channel allocation mode are not uniform among different devices. Such differences often lead to difficulties in the implementation of the same type of interface circuit in different products. Under the prior art condition, in order to adapt to the different interface types, the number and the backup modes, related equipment often needs to redesign or greatly modify a Printed Circuit Board (PCB) according to specific projects, so that the workload of design, verification and production is increased, and meanwhile, the universalization degree and the maturity of products are limited because board-level design is difficult to reuse. Disclosure of Invention The invention provides a dual-interface satellite-borne signal receiving and transmitting system, which aims to solve the technical problems that in the prior art, a conventional satellite-borne signal receiving and transmitting system is required to be frequently redesigned, and the universalization degree and reliability of a PCB are difficult to improve due to the differences of interface types, the number, the receiving and transmitting directions and the redundant backup modes. In order to solve the problems, the technical scheme of the invention is that the dual-interface satellite-borne signal receiving and transmitting system at least comprises two groups of mutually independent and redundantly configured signal receiving and transmitting channels, and any signal receiving and transmitting channel comprises: The receiving-transmitting interface chip assembly is used for realizing the transmission and/or the reception of differential signals; the external interface is used for being electrically connected with a differential connector outside the satellite-borne equipment; the peripheral configurable circuit is respectively and electrically connected with the receiving-transmitting interface chip assembly and the external interface and is used for carrying out coupling, impedance matching, amplitude limiting protection and/or fault isolation on the signal receiving-transmitting channel based on different configuration conditions; And the controller is electrically connected with the transceiver interface chip assembly through the peripheral configurable circuit and is used for enabling acquisition processing or transmission processing of differential data. Preferably, the transceiver interface chips in the transceiver interface chip assembly can be selectively configured into LVDS transceiver interface chips or RS422 transceiver interface chips with the same power supply voltage and compatible packaging and different pins; The receiving and transmitting interface chip component reserves a shared packaging bonding pad for installing the LVDS receiving and transmitting interface chip and the RS422 receiving and transmitting interface chip on the same printed board of the satellite-borne signal receiving and transmitting system; The transceiver interface chip assembly is configured to selectively load and unload the LVDS transceiver interface chip and the RS422 transceiver interface chip to switch LVDS interface and RS422 interface functions of the satellite-borne signal transceiver system. Preferably, the packaging mode of the LVDS transceiver interface chip and the RS422 transceiver interface chip includes forward molding and reverse molding to form two pin sequences, namely clockwise and anticlockwise; The printed board is configured such that the front side thereof is mounted with the transceiver interface chip of the front molding package and the back side thereof is mounted with t