CN-122027046-A - Test circuit, test method of data transceiver circuit and integrated circuit

CN122027046ACN 122027046 ACN122027046 ACN 122027046ACN-122027046-A

Abstract

The embodiment of the invention discloses a test circuit, a test method of a data transceiver circuit and an integrated circuit. In the embodiment of the invention, the output received data sequence is checked on one side of a tested data receiving and transmitting circuit in the test flow, so that the state transition mode of continuous multiple bits of the received data sequence is determined through the sliding window interception based on the bit state sequence obtained by the check, and the occurrence times of all possible state transition modes in the data sequence are recorded, so that a transition state matrix capable of describing the channel attribute and the error code performance is obtained. Therefore, a tester can further evaluate and calculate relevant parameters of error code performance based on the recorded transition state matrix more quickly and accurately. Further, testing may be further facilitated by integrating the test circuit in an integrated circuit.

Inventors

CHEN YANBIN
REN NAN
LIU HUAN

Assignees

北京平头哥信息技术有限公司

Dates

Publication Date: 20260512
Application Date: 20260129

Claims (14)

1. A test circuit for detecting a data transceiver circuit, the data transceiver circuit obtaining a received data sequence through a physical transmission channel and performing error correction code decoding on the received data sequence to output a decoded data sequence, the test circuit comprising: The test data checker is connected to the data receiving and transmitting circuit and is used for checking each bit of the received data sequence in a test flow, determining the bit state of each bit in the received data sequence, and outputting a bit state sequence corresponding to the received data sequence, wherein the bit state is used for representing the correctness or the error of the received data of the corresponding bit; a transfer mode determining circuit, configured to determine two adjacent bit state subsequences in the bit state sequence, and determine a transfer mode of the bit state subsequence, where the adjacent bit state subsequence is determined at an adjacent position through a sliding window moving along the bit state sequence, and a length of the bit state subsequence is greater than or equal to 2; And the write circuit is used for counting corresponding transfer mode data items in a preset state transfer matrix according to the transfer modes of the bit state subsequence, wherein the state transfer matrix is used for recording count values of all different transfer modes of the bit state subsequence so as to describe channel attributes of a physical transmission channel, and the channel attributes are used for evaluating the error correction performance of the error correction decoding.
2. The test circuit of claim 1, wherein the test circuit further comprises: a memory for storing the state transition matrix; Or alternatively The test circuit stores the state transition matrix using a memory of the data transceiver circuit.
3. The test circuit of claim 1, wherein the two adjacent bit state subsequences include a first bit state subsequence and a second bit state subsequence that is earlier in the bit state sequence, the first bit state subsequence being a bit state subsequence within a window when the sliding window is in a first position, the second bit state subsequence being a bit state subsequence within a window when the sliding window is slid back one predetermined step, the transition pattern characterizing a transition of the first bit state subsequence to the second bit state subsequence.
4. The test circuit of claim 1, wherein the test data checker is a pseudo-random binary sequence checker and the received data sequence is a pseudo-random binary sequence.
5. The test circuit of claim 1, wherein the test circuit is integrated in the same integrated circuit as the data transceiver circuit.
6. An integrated circuit, the integrated circuit comprising: A data receiving and transmitting circuit for obtaining a received data sequence through a physical transmission channel, performing error correction code decoding on the received data sequence to output a decoded data sequence, and A test circuit as claimed in any one of claims 1 to 5.
7. A method for testing a data transceiver circuit, the method comprising: Acquiring a received data sequence through a physical transmission channel, wherein the received data sequence is a data sequence before error correction decoding by a physical layer; Each bit of the received data sequence is checked, the bit state of each bit in the received data sequence is determined, a bit state sequence corresponding to the received data sequence is output, and the bit state is used for representing the correctness or the error of the received data of the corresponding bit; Determining two adjacent bit state subsequences in the bit state sequence, and determining a transfer mode of the bit state subsequences, wherein the adjacent bit state subsequences are determined at adjacent positions through a sliding window moving along the bit state sequence, and the length of the bit state subsequences is more than or equal to 2; And counting corresponding transfer mode data items in a preset state transfer matrix according to the transfer modes of the bit state subsequence, wherein the state transfer matrix is used for recording count values of all different transfer modes of the bit state subsequence so as to describe channel attributes of a physical transmission channel, and the channel attributes are used for evaluating the error correction performance of the error correction decoding.
8. The method of claim 7, further comprising continuing to count transfer mode data items until normalized data for each data item in the state transfer matrix stabilizes, the normalized data stabilizing referring to a change in the normalized data after a predetermined number of updates being less than a predetermined error threshold.
9. The method of claim 8, further comprising reading the state transition matrix in response to the normalized data for each data item in the state transition matrix being stable; And calculating at least one of error code transmission probability, error rate, frame error rate, block error rate, symbol error rate or error rate after error correction according to the state transition matrix.
10. The method of claim 7, wherein the two adjacent bit state subsequences include a first bit state subsequence and a second bit state subsequence that is earlier in the bit state sequence, the first bit state subsequence being a bit state subsequence within a window when the sliding window is in a first position, the second bit state subsequence being a bit state subsequence within a window when the sliding window is slid back one predetermined step, the transition pattern characterizing a transition of the first bit state subsequence to the second bit state subsequence.
11. The method of claim 7, wherein the received data is a pseudo-random binary sequence; Each bit of the received data sequence is checked, specifically: Generating a check sequence to check each bit of the received data sequence according to a pseudo-random binary sequence generation algorithm.
12. The method of claim 7, wherein at least some of the steps of the method are implemented by hardware circuitry integrated in the same integrated circuit as the data transceiver circuitry, or The method is implemented by a computer program.
13. A computer readable storage medium, characterized in that the computer readable storage medium has stored therein a computer program which, when executed by a processor, implements the method according to any of claims 7-11.
14. An integrated circuit, the integrated circuit comprising: A data transceiver circuit for acquiring the received data sequence via the physical transmission channel, performing error correction code decoding on the received data sequence to output a decoded data sequence, and A memory for storing one or more computer program instructions, and a processing core, wherein the one or more computer program instructions are executed by the processing core to implement the method of any of claims 7-11.

Description

Test circuit, test method of data transceiver circuit and integrated circuit Technical Field The present invention relates to the field of circuit testing, and in particular, to a testing circuit, a testing method for a data transceiver circuit, and an integrated circuit. Background With the rapid development of bus technology and network communication technology, the signal transmission rate between different devices and different circuits is continuously increasing. For example, the communication protocol family PCIe/UALink/Ethernet 802.3/CXL, etc., has promulgated a new generation of high-speed communication protocols. In the new high-speed communication protocol, the buses or network protocols can directly support the error correction code coding technology in the physical layer, namely, the function of error correction code coding and decoding is embedded in the physical layer, so that the problem of error rate degradation caused by continuous increase of the rate can be solved. Meanwhile, the performance of the existing error correction codes is stronger and stronger, and by taking RS-FEC (Reed-Solomon Forward Error Correction, reed-Solomon forward error correction code) as an example, the error rate after error correction can be reduced by a plurality of orders of magnitude. Since the bit error rate is too low, enough data needs to be detected by accumulating test runs for a long enough time, which makes it difficult to quickly and accurately test and evaluate the performance of the error code after error correction for a circuit supporting a high-speed communication protocol and having an error correction coding and decoding technology embedded in a physical layer. Disclosure of Invention In view of this, the embodiments of the present invention provide a test circuit, a test method for a data transceiver circuit, and an integrated circuit, which are expected to perform faster and more accurate error performance test and evaluation for the data transceiver circuit with error correction code decoding capability. In a first aspect, a test circuit is provided for detecting a data transceiver circuit, where the data transceiver circuit obtains a received data sequence through a physical transmission channel, and performs error correction code decoding on the received data sequence to output a decoded data sequence, and the test circuit includes: The test data checker is connected to the data receiving and transmitting circuit and is used for checking each bit of the received data sequence in a test flow, determining the bit state of each bit in the received data sequence, and outputting a bit state sequence corresponding to the received data sequence, wherein the bit state is used for representing the correctness or the error of the received data of the corresponding bit; a transfer mode determining circuit, configured to determine two adjacent bit state subsequences in the bit state sequence, and determine a transfer mode of the bit state subsequence, where the adjacent bit state subsequence is determined at an adjacent position through a sliding window moving along the bit state sequence, and a length of the bit state subsequence is greater than or equal to 2; And the write circuit is used for counting corresponding transfer mode data items in a preset state transfer matrix according to the transfer modes of the bit state subsequence, wherein the state transfer matrix is used for recording count values of all different transfer modes of the bit state subsequence so as to describe channel attributes of a physical transmission channel, and the channel attributes are used for evaluating the error correction performance of the error correction decoding. In some embodiments, the test circuit further comprises: a memory for storing the state transition matrix; Or alternatively The test circuit stores the state transition matrix using a memory of the data transceiver circuit. In some embodiments, the two adjacent bit state subsequences include a first bit state subsequence and a second bit state subsequence that is earlier in the bit state sequence, the first bit state subsequence being a bit state subsequence within a window when the sliding window is in a first position, the second bit state subsequence being a bit state subsequence within a window when the sliding window is slid back by a predetermined step, the transition mode characterizing a transition of the first bit state subsequence to the second bit state subsequence. In some embodiments, the test data checker is a pseudo-random binary sequence checker and the received data sequence is a pseudo-random binary sequence. In some embodiments, the test circuit is integrated in the same integrated circuit as the data transceiver circuit. In a second aspect, there is provided an integrated circuit comprising: A data receiving and transmitting circuit for obtaining a received data sequence through a physical transmission channel, performing error correcti