CN-122027061-A - FPGA-based Lais channel simulation method, system and chip

CN122027061ACN 122027061 ACN122027061 ACN 122027061ACN-122027061-A

Abstract

The invention relates to the technical field of wireless communication, in particular to a Lais channel simulation method, a Lais channel simulation system and a Lais channel simulation chip based on an FPGA, wherein the method comprises the steps of generating time slices according to maximum Doppler frequency shift, initializing Doppler frequency shift parameters of all scattering paths, generating direct path complex envelopes in each time slice and synchronously generating multiple scattering path complex envelopes according to current parameters, updating Doppler frequency shift parameters of the scattering paths at the end of each time slice, calculating amplitude coefficients based on Lais factors and simulated propagation delays of all scattering paths, performing amplitude modulation, and synthesizing and outputting all path complex envelopes. According to the invention, the real-time calculation burden of the FPGA is reduced through a time slicing mechanism, and the power distribution is performed based on a radar equation, so that the simulation result is more in line with the real channel characteristics.

Inventors

HUANG XIAOQIN
HUANG YIPING
CHEN JUN
ZHANG LING
LI ZHENCHUAN

Assignees

成都富元辰科技有限公司

Dates

Publication Date: 20260512
Application Date: 20260408

Claims (10)

1. A method for simulating a rice channel based on an FPGA, wherein the following steps are performed on the FPGA: s1, generating a plurality of time slices according to the maximum Doppler frequency shift; s2, initializing Doppler frequency shift parameters of each scattering path and storing the Doppler frequency shift parameters into a register of the FPGA; s3, generating a direct path simulation signal with fixed Doppler frequency shift in each time slice, and synchronously generating a plurality of scattering path simulation signals according to Doppler frequency shift parameters in a current register; s4, updating Doppler frequency shift parameters of a plurality of scattering paths in a register when each time slice is finished, and taking the Doppler frequency shift parameters as parameter configuration of the next time slice; S5, calculating amplitude coefficients of a direct path and each scattering path based on a preset Lais factor and analog propagation delay of each scattering path, and performing amplitude modulation; S6, synthesizing all the direct path simulation signals subjected to amplitude modulation with the scattering path simulation signals, and outputting the rice channel simulation signals.
2. The method for simulating a Less channel based on an FPGA as claimed in claim 1, wherein the step S1 is specifically to take the inverse of the maximum Doppler shift as the duration of each time slice, and generate a series of consecutive time slices.
3. The method for simulating the Less channel based on the FPGA according to claim 2, wherein in S2, doppler shift parameters of each scattering path are initialized, specifically, an initial Doppler shift value is generated for each scattering path through a pseudo-random number generator in the FPGA, and the initial Doppler shift value is stored in a corresponding register.
4. The method for simulating a Less channel based on an FPGA of claim 3, wherein in S3, a direct path simulation signal with a fixed Doppler shift is generated, specifically, a direct path Doppler shift value is calculated according to a preset moving speed, a signal wavelength and a direct wave incident angle, the direct path Doppler shift value is converted into a frequency control word, and then the frequency control word is input into a fixed parameter digital oscillator, so that a direct path simulation signal in the form of a complex signal is generated.
5. The method for simulating a Less channel based on an FPGA as claimed in claim 4, wherein in S4, the Doppler shift parameters of the plurality of scattering paths in the register are updated, specifically, a new Doppler shift value is calculated for each scattering path by the parameter updater, and written into the corresponding register to cover the original value.
6. The method for simulating a rice channel based on an FPGA of claim 5, wherein in S5, the calculating the amplitude coefficient of each scattering path specifically includes: determining an additional delay of each scattering path relative to the reference path; Determining that the power distribution weight of each scattering path is inversely proportional to the square of the additional delay according to a physical rule that the power is inversely proportional to the square of the propagation distance; determining the total power of all scattering paths according to the Lees factor; and distributing the total power to each scattering path according to the power distribution weight, and converting the total power into a corresponding amplitude coefficient.
7. The FPGA-based rice channel simulation method of claim 6, wherein the magnitude coefficients of the scattering paths are expressed as: , Where P i is the power of the ith scattering path, P all is the total power of all scattering paths, R is the initial propagation distance of the reference path, I is the total number of scattering paths, Δr i is the additional propagation distance of the ith scattering path relative to the reference path, and Δr i is the additional propagation distance of the ith scattering path relative to the reference path.
8. The FPGA-based rice channel simulation method of claim 1, wherein the number of scattering paths is greater than or equal to three.
9. An FPGA-based rice channel simulation system for implementing the method of any one of claims 1 to 8, the system being integrated within an FPGA chip, comprising: the time sequence control module is used for generating a time slice control signal according to the maximum Doppler frequency shift; The direct path generation module is used for generating a direct path simulation signal with fixed Doppler frequency shift; The scattering path generation and control module is in communication connection with the time sequence control module and is used for initializing and storing Doppler frequency shift parameters of each scattering path, generating a plurality of scattering path simulation signals in each time slice and updating the Doppler frequency shift parameters at the end of each time slice; The power distribution and synthesis module is in communication connection with the direct path generation module and the scattering path generation and control module and is used for calculating the amplitude coefficient of each path based on a preset Lais factor and the analog propagation delay of each scattering path, carrying out amplitude modulation and synthesis on each path simulation signal and outputting a Lais channel simulation signal.
10. An FPGA chip characterized by its internal configuration with programmable logic circuits programmed to implement the FPGA-based rice channel simulation system as claimed in claim 9.

Description

FPGA-based Lais channel simulation method, system and chip Technical Field The invention relates to the technical field of wireless communication, in particular to a method, a system and a chip for simulating a Lees channel based on an FPGA. Background The fading characteristics of a wireless channel are one of the key factors affecting the performance of a communication system. Of the small-scale fading channels, the rice fading channel and the rayleigh fading channel are the two most common models. Rayleigh fading channels are suitable for multipath propagation scenarios without direct paths, while rice fading channels are suitable for scenarios where there is a strong direct path and multiple reflection/scattering paths at the same time, and the amplitude of the received signal follows rice distribution. When the rice factor K is 0, the rice fading channel is degenerated to a rayleigh fading channel. The classical rice channel model proposed by Clarke in 1968 is considered as a reference model for wireless channel modeling, and its two-dimensional impulse response can be expressed as a superposition of infinite paths. However, this model requires an infinite number of oscillators, resulting in its inability to be directly implemented on a software or hardware platform. To solve this problem, a sine wave superposition method (such as iakes model) is generally used in the prior art to approximate the rice channel, i.e., a complex gaussian process is approximated by the sum of a finite number of sine waves. In terms of hardware implementation, the prior art (such as CN105049142 a) discloses a dual-channel static baseband channel simulation device, which adopts a structure of pc+dsp+fpga, a user can select a channel model (including rice fading) and configure parameters at an upper computer, the parameters are fixed by DSP and then transmitted to FPGA, and the FPGA applies multipath delay, loss, fading and noise to an input signal according to the received parameters. However, the general channel simulator has the following defects that firstly, the implementation mode of a rice channel is not optimized by hardware aiming at the characteristics of the model, and the FPGA resource consumption is large due to the fact that the hardware translation of a mathematical formula is directly adopted, secondly, when a high-speed moving scene needs to be simulated in real time, the computing architecture is difficult to meet the real-time requirement, and thirdly, the physical propagation rule is not considered in the power distribution of a scattering path, and the physical reality of a simulation result is to be improved. Disclosure of Invention The invention aims to solve the problems in the prior art and provides a method, a system and a chip for simulating a Lees channel based on an FPGA. In order to achieve the above purpose, the technical scheme adopted by the invention is as follows: a Less channel simulation method based on an FPGA performs the following steps on the FPGA: s1, generating a plurality of time slices according to the maximum Doppler frequency shift; s2, initializing Doppler frequency shift parameters of each scattering path and storing the Doppler frequency shift parameters into a register of the FPGA; s3, generating a direct path simulation signal with fixed Doppler frequency shift in each time slice, and synchronously generating a plurality of scattering path simulation signals according to Doppler frequency shift parameters in a current register; s4, updating Doppler frequency shift parameters of a plurality of scattering paths in a register when each time slice is finished, and taking the Doppler frequency shift parameters as parameter configuration of the next time slice; S5, calculating amplitude coefficients of a direct path and each scattering path based on a preset Lais factor and analog propagation delay of each scattering path, and performing amplitude modulation; S6, synthesizing all the direct path simulation signals subjected to amplitude modulation with the scattering path simulation signals, and outputting the rice channel simulation signals. Further, the step S1 specifically includes taking the inverse of the maximum Doppler shift as the duration of each time slice, and generating a series of continuous time slices. Further, in the step S2, doppler frequency shift parameters of each scattering path are initialized, specifically, an initial Doppler frequency shift value is generated for each scattering path through a pseudo random number generator in the FPGA, and the initial Doppler frequency shift values are stored in a corresponding register. Further, in the step S3, a direct path simulation signal with fixed Doppler frequency shift is generated, specifically, a direct path Doppler frequency shift value is calculated according to a preset moving speed, a preset signal wavelength and a preset direct wave incident angle, the direct path Doppler frequency shift value is converted