CN-122027086-A - Line coding and decoding method and device based on scrambling and dynamic programming

CN122027086ACN 122027086 ACN122027086 ACN 122027086ACN-122027086-A

Abstract

The invention provides a line coding and decoding method and device based on scrambling and dynamic programming, and relates to the technical field of line coding. The method comprises the steps of obtaining an original data packet, setting the order of a binary scrambling code polynomial according to the length of the original data packet, constructing the binary scrambling code polynomial, generating a scrambling code table matrix, carrying out first-stage scrambling on the original data packet according to the scrambling code table matrix, a maximum processing round parameter and a bit detection threshold value, generating temporary data payload and a first-stage scrambling round counting variable, carrying out second-stage scrambling on the temporary data payload, generating the data payload and a second-stage scrambling round counting variable, further generating an encoded data packet, carrying out bit-by-bit analysis on the encoded data packet, obtaining the data payload to be decoded, the first-stage scrambling code and the second-stage scrambling round counting variable, carrying out decoding operation on the data payload to be decoded, and outputting the decoded data packet. The method is used for effectively inhibiting the occurrence probability of the long continuous homovalued bit sequence so as to improve the reliability of signal transmission.

Inventors

SU RINA
Xi Xiwen
SUN QIFU

Assignees

北京科技大学

Dates

Publication Date: 20260512
Application Date: 20260309

Claims (10)

1. A line coding and decoding method based on scrambling and dynamic programming, the method comprising: S1, acquiring a plurality of original data packets to be encoded, setting the order of a binary scrambling code polynomial according to the length of the original data packets, setting bit detection thresholds and maximum processing round parameters of a first-stage scrambling code and a second-stage scrambling code, initializing round counting variables of the first-stage scrambling code and the second-stage scrambling code; S2, constructing a binary scrambling code polynomial according to the selected multi-order binary primitive polynomial and the set order of the binary scrambling code polynomial, and generating a scrambling code table matrix according to the binary scrambling code polynomial; s3, obtaining any original data packet to be encoded, and carrying out first-stage scrambling on the obtained original data packet according to a scrambling table matrix, a maximum processing round parameter of the first-stage scrambling and a bit detection threshold value to generate a temporary data payload and an updated first-stage scrambling round counting variable, wherein the length of the temporary data payload is the length of the original data packet; S4, judging whether second-stage scrambling is carried out according to the maximum processing round parameter of the second-stage scrambling, if so, carrying out second-stage scrambling on the temporary data payload according to the scrambling code table matrix, the maximum processing round parameter of the second-stage scrambling and the bit detection threshold value, and generating a data payload and an updated second-stage scrambling round counting variable, wherein the length of the data payload is the length of an original data packet; s5, combining preset jump edge flag bits, and generating a coded data packet according to the data payload, the updated first-stage scrambling code and the updated second-stage scrambling code round counting variable, wherein the length of the coded data packet is the sum of the length of the original data packet, the maximum processing round parameter of the first-stage scrambling code, the maximum processing round parameter of the second-stage scrambling code and the number of the jump edge flag bits; s6, carrying out bit-by-bit analysis on the coded data packet to obtain data payload to be decoded, a first-stage scrambling code and a second-stage scrambling code round counting variable; S7, decoding the data payload to be decoded according to the scrambling code table matrix, the first-stage scrambling code and the second-stage scrambling code round counting variable, and outputting a decoded data packet.
2. The scrambling and dynamic programming based line coding and decoding method according to claim 1, wherein S2 comprises: s21, constructing a binary scrambling polynomial according to the selected multi-order binary primitive polynomial and the order of the set binary scrambling polynomial, initializing a multi-bit shift register state vector to be an all-1 sequence, initializing a scrambling table matrix to be an all-zero matrix, and enabling ; S22, sequentially storing the numerical values in the state vector of the multi-bit shift register to the first scrambling code table matrix A row; S23, order Judging Whether or not the step is true, if true, the step S24 is executed, and if false, the step S25 is executed, wherein, The order of the binary scrambling polynomial; S24, updating a multi-bit shift register state vector based on the shift register, and turning to execute the step S22; s25, outputting a scrambling code table matrix, wherein the scrambling code table matrix comprises Lines, each line Bits.
3. The scrambling and dynamic programming based line coding and decoding method according to claim 1, wherein S3 comprises: S31, any original data packet to be coded is obtained, and a temporary data payload is initialized according to the obtained original data packet, wherein the length of the temporary data payload is the length of the original data packet; S32, calculating the maximum processing round of the first-stage scrambling code according to the maximum processing round parameter of the first-stage scrambling code, and enabling the counting variable of the first-stage scrambling code round to be 0; s33, detecting whether a bit detection threshold bit length reaching or exceeding a first-stage scrambling code exists in the temporary data payload and a value sequence exists, if so, executing a step S34, and if not, executing a step S37; s34, generating a first-stage scrambling code sequence based on the scrambling code table matrix, the acquired serial number of the original data packet and the current first-stage scrambling code round counting variable; s35, carrying out bit exclusive OR on the temporary data payload and the first-stage scrambling code sequence to generate an updated temporary data payload; s36, updating a first-stage scrambling code round counting variable, judging whether the updated first-stage scrambling code round counting variable is smaller than the maximum processing round of the first-stage scrambling code, if so, turning to execute the step S33, and if not, executing the step S37; S37, outputting temporary data payload and the updated first-stage scrambling code round counting variable.
4. The scrambling and dynamic programming based line coding and decoding method according to claim 1, wherein S4 comprises: S41, judging whether the maximum processing round parameter of the second-stage scrambling code is 0, if so, setting the round counting variable of the second-stage scrambling code to be 0, executing the step S48, and if not, executing the step S42; s42, initializing a data payload according to the temporary data payload, wherein the length of the data payload is the length of an original data packet; S43, calculating the maximum processing round of the second-stage scrambling code according to the maximum processing round parameter of the second-stage scrambling code, and enabling the counting variable of the second-stage scrambling code round to be 0; s44, detecting whether a bit detection threshold bit length reaching or exceeding the second-level scrambling code exists in the data payload and a value sequence exists, if so, executing a step S45, and if not, executing a step S48; s45, generating a second-stage scrambling code sequence based on the scrambling code table matrix, the acquired sequence number of the original data packet, the updated first-stage scrambling code round counting variable and the current second-stage scrambling code round counting variable; S46, carrying out bit exclusive OR on the data payload and the second-stage scrambling sequence to generate updated data payload; S47, updating a second-stage scrambling code round counting variable, judging whether the updated second-stage scrambling code round counting variable is smaller than the second-stage scrambling code maximum processing round, if so, turning to execute the step S44, and if not, executing the step S48; s48, outputting the data payload and the updated second-stage scrambling code round counting variable.
5. The scrambling and dynamic programming based line coding and decoding method according to claim 1, wherein S5 comprises: S51, setting a packet header according to the updated binary representation of the first-stage scrambling code round counting variable, wherein the length of the packet header is the maximum processing round parameter bit of the first-stage scrambling code; s52, judging whether the maximum processing round parameter of the second-stage scrambling code is greater than or equal to 1, if so, setting a packet tail according to the updated second-stage scrambling code round counting variable, wherein the length of the packet tail is the maximum processing round parameter bit of the second-stage scrambling code; s53, combining preset jump edge marking bits, and obtaining a coded data packet according to a data payload, a packet header and a packet tail, wherein the length of the coded data packet is the sum of the original data packet length, the maximum processing round parameter of the first-stage scrambling code, the maximum processing round parameter of the second-stage scrambling code and the number of the jump edge marking bits.
6. The scrambling and dynamic programming based line coding and decoding method according to claim 1, wherein S6 comprises: S61, intercepting bits corresponding to the maximum processing round parameters of the first-stage scrambling codes from preset positions of the coded data packet, and calculating updated first-stage scrambling code round counting variables; S62, judging whether the maximum processing round parameter of the second-stage scrambling code is greater than or equal to 1, if so, intercepting bits corresponding to the maximum processing round parameter of the second-stage scrambling code from a preset position of the coded data packet, and calculating an updated second-stage scrambling code round counting variable; S63, setting data payload to be decoded according to the coded data packet.
7. The scrambling and dynamic programming based line coding and decoding method according to claim 1, wherein S7 comprises: S71, calculating a total reverse scrambling code round counting variable based on the sum of the updated first-stage scrambling code round counting variable and the updated second-stage scrambling code round counting variable, judging whether the total reverse scrambling code round counting variable is 0 or not, if so, executing a step S76, otherwise, executing a step S72; S72, enabling the total reverse scrambling code round counting variable to be 0; s73, generating a scrambling code sequence based on a scrambling code table matrix, the sequence number of the coded data packet and the current total reverse scrambling code round counting variable; s74, carrying out bit exclusive OR on the data payload to be decoded and the scrambling sequence to generate updated data payload; S75, updating a total reverse scrambling code round counting variable, judging whether the updated total reverse scrambling code round counting variable is smaller than a value obtained by subtracting one from the sum of the updated first-stage scrambling code round counting variable and the second-stage scrambling code round counting variable, if so, turning to execute the step S73, otherwise, executing the step S76; s76, obtaining a decoded data packet according to the updated data payload and outputting the decoded data packet.
8. A scrambling and dynamic programming-based line coding and decoding device for implementing a scrambling and dynamic programming-based line coding and decoding method according to any one of claims 1 to 7, characterized in that the device comprises: The data acquisition module is used for acquiring a plurality of original data packets to be encoded, setting the order of a binary scrambling code polynomial according to the length of the original data packets, setting the bit detection threshold value and the maximum processing round parameter of the first-stage scrambling code and the second-stage scrambling code; the scrambling code table pre-generation module is used for constructing a binary scrambling code polynomial according to the selected multi-order binary primitive polynomial and the set order of the binary scrambling code polynomial and generating a scrambling code table matrix according to the binary scrambling code polynomial; The first-stage scrambling module is used for obtaining any original data packet to be encoded, carrying out first-stage scrambling on the obtained original data packet according to the scrambling table matrix, the maximum processing round parameter of the first-stage scrambling and the bit detection threshold value, and generating temporary data payload and updated first-stage scrambling round counting variable, wherein the length of the temporary data payload is the length of the original data packet; The second-stage scrambling module is used for judging whether to perform second-stage scrambling according to the maximum processing round parameter of the second-stage scrambling, and if so, performing second-stage scrambling on the temporary data payload according to the scrambling table matrix, the maximum processing round parameter of the second-stage scrambling and the bit detection threshold value to generate a data payload and an updated second-stage scrambling round counting variable, wherein the length of the data payload is the length of an original data packet; The code data packet generation module is used for combining preset jump edge flag bits, and generating code data packets according to data payloads, updated first-stage scrambling codes and second-stage scrambling code turn count variables, wherein the length of the code data packets is the sum of the length of original data packets, the maximum processing turn parameters of the first-stage scrambling codes, the maximum processing turn parameters of the second-stage scrambling codes and the number of the jump edge flag bits; The coded data packet analysis module is used for carrying out bit-by-bit analysis on the coded data packet to obtain a data payload to be decoded, a first-stage scrambling code and a second-stage scrambling code round counting variable; And the decoding data packet output module is used for performing decoding operation on the data payload to be decoded according to the scrambling code table matrix, the first-stage scrambling code and the second-stage scrambling code round counting variable and outputting a decoding data packet.
9. A line coding and decoding device based on scrambling and dynamic programming, characterized in that the line coding and decoding device based on scrambling and dynamic programming comprises: A processor; a memory having stored thereon computer readable instructions which, when executed by the processor, implement the method of any of claims 1 to 7.
10. A computer readable storage medium having stored therein program code which is callable by a processor to perform the method of any one of claims 1 to 7.

Description

Line coding and decoding method and device based on scrambling and dynamic programming Technical Field The invention relates to the technical field of line coding in the technical field of data coding and transmission, in particular to a line coding and decoding method and device based on scrambling and dynamic programming, which are suitable for high-reliability and high-efficiency data processing scenes such as digital communication. Background With the rapid development of display technology toward high resolution and high refresh rate, the transmission rate of the high-speed serial interface between the TCON (Timing Controller ) as a core transmission channel and the source driver is continuously increasing. In this context, signal integrity, clock synchronization, and bit error rate control issues are increasingly prominent. Particularly, the long and value bit sequence in the data stream is very easy to cause the lock losing of the clock data recovery circuit of the receiving end, thereby causing communication interruption or increase of the error rate. To solve the above problems, the related art generally adopts a scrambling code or a line coding scheme. Although the conventional (Linear Feedback SHIFT REGISTER ) scrambling technique does not increase the overhead of extra bandwidth, it cannot deterministically eliminate long-connection sequences in the worst data mode, and it is difficult to fully guarantee the communication reliability. Line coding techniques (e.g., 8b/10b coding), while guaranteeing the hopping density, introduce up to 20% bandwidth overhead, limiting the effective transmission throughput. Therefore, a new binary data encoding and decoding method capable of effectively suppressing the occurrence of long-duration bit sequences and maintaining high encoding efficiency while ensuring clock synchronization and data reliability is needed to meet the performance requirements in the data communication scenario. Disclosure of Invention In order to solve the problem of low traditional line coding efficiency in the prior art, the embodiment of the invention provides a line coding and decoding method and device based on scrambling and dynamic programming. The technical scheme is as follows: In one aspect, a method for coding and decoding a line based on scrambling and dynamic programming is provided, the method is implemented by a line coding and decoding device based on scrambling and dynamic programming, and the method includes: s1, acquiring a plurality of original data packets to be encoded, setting the order of a binary scrambling code polynomial according to the length of the original data packets, setting bit detection thresholds and maximum processing round parameters of a first-stage scrambling code and a second-stage scrambling code, and initializing round counting variables of the first-stage scrambling code and the second-stage scrambling code. S2, constructing a binary scrambling polynomial according to the selected multi-order binary primitive polynomial and the set order of the binary scrambling polynomial, and generating a scrambling table matrix according to the binary scrambling polynomial. S3, obtaining any original data packet to be encoded, and carrying out first-stage scrambling on the obtained original data packet according to the scrambling table matrix, the maximum processing round parameter of the first-stage scrambling and the bit detection threshold value, so as to generate a temporary data payload and an updated first-stage scrambling round counting variable, wherein the length of the temporary data payload is the length of the original data packet. S4, judging whether second-stage scrambling is carried out according to the maximum processing round parameter of the second-stage scrambling, and if so, carrying out second-stage scrambling on the temporary data payload according to the scrambling code table matrix, the maximum processing round parameter of the second-stage scrambling and the bit detection threshold value to generate a data payload and an updated second-stage scrambling round counting variable, wherein the length of the data payload is the length of an original data packet. S5, combining preset jump edge flag bits, and generating a coded data packet according to the data payload, the updated first-stage scrambling code and the updated second-stage scrambling code round counting variable, wherein the length of the coded data packet is the sum of the length of the original data packet, the maximum processing round parameter of the first-stage scrambling code, the maximum processing round parameter of the second-stage scrambling code and the number of the jump edge flag bits. S6, analyzing the coded data packet bit by bit to obtain data payload to be decoded, primary scrambling code and secondary scrambling code round counting variables. S7, decoding the data payload to be decoded according to the scrambling code table matrix, the first-stage scramblin