CN-122027389-A - Interconnection bus interleave access method, device, terminal and medium

CN122027389ACN 122027389 ACN122027389 ACN 122027389ACN-122027389-A

Abstract

The application provides an access method, device, terminal and medium of an interconnection bus interleave. The method is applied to a network-on-chip-based communication system, and the communication system comprises a network-on-chip, a plurality of master devices and a plurality of slave devices, wherein the master devices and the slave devices are respectively connected with the network-on-chip. The method comprises the steps of configuring the network-on-chip by adding an auxiliary decoding space on the basis of a reference decoding space of the network-on-chip or adding a plurality of decoding spaces with different interleaving granularities from the reference decoding space, and completing interleave access of the corresponding slave device through the configured network-on-chip based on a space mapping rule when the master device initiates a bus transaction. The application improves the stride access efficiency under low-order interleaving.

Inventors

Diao Junqiang
HUANG WEI

Assignees

奕行智能科技(广州)有限公司

Dates

Publication Date: 20260512
Application Date: 20260113

Claims (10)

1. An interconnection bus interleave access method is applied to a network-on-chip-based communication system, the communication system comprises a network-on-chip and a plurality of master devices and a plurality of slave devices respectively connected with the network-on-chip, and the method is characterized by comprising the following steps: Configuring the network on chip by adding an auxiliary decoding space on the basis of a reference decoding space of the network on chip or adding a plurality of decoding spaces with different interleaving granularities from the reference decoding space; when the master device initiates a bus transaction, the corresponding slave device interleave access is completed through the configured network-on-chip based on the space mapping rule.
2. The method for accessing the interconnection bus interleave according to claim 1, wherein the types of the spatial mapping rules include a first spatial mapping rule and a second spatial mapping rule, and when the master initiates a bus transaction, based on the spatial mapping rule, the method for completing interleave access of the corresponding slave through the configured network-on-chip includes: When a main device initiates a bus transaction, based on a first space mapping rule, a reference decoding space is used for completing interleave access of a corresponding slave device under the assistance of an auxiliary decoding space; Or alternatively When the master initiates a bus transaction, interleave accesses of the corresponding slave are completed by using the decoding space determined in the reference decoding space and each decoding space based on the second space mapping rule.
3. The method for accessing the interconnect bus interleave according to claim 2, wherein when the master initiates the bus transaction, the master completes interleave access of the corresponding slave through the reference decoding space and with the aid of the auxiliary decoding space based on the first space mapping rule, including: When a main device initiates a current bus transaction, determining a transmission channel which is initially allocated to the current bus transaction in the on-chip network based on a low-order address carried by the current bus transaction according to the interleaving granularity of a reference decoding space; Judging whether the transmission channel initially allocated to the current bus transaction is consistent with the final transmission channel of the last bus transaction; If the transmission channels are inconsistent, mapping the current bus transaction to a corresponding auxiliary decoding space for decoding based on a first space mapping rule so as to determine the final transmission channel of the current bus transaction in the on-chip network; And sending the current bus transaction to the corresponding slave device through the final transmission channel of the current bus transaction so as to finish the access of the slave device.
4. The method of claim 3, wherein mapping the current bus transaction onto the corresponding auxiliary decoding space based on the first spatial mapping rule comprises: Based on the first space mapping rule, the low-order address carried by the current bus transaction and the head address of the auxiliary decoding space, generating a corresponding mapping low-order address, and updating the mapping low-order address into the low-order address carried by the current bus transaction.
5. The method according to claim 4, wherein the mapping information is generated by mapping the current bus transaction to the corresponding auxiliary decoding space, and the final transmission channel of the current bus transaction simultaneously transmits the current bus transaction and the mapping information to the corresponding slave device, wherein the mapping information is generated by generating the corresponding mapping information based on the low-order addresses before and after updating the current bus transaction, and wherein the number of bits of the mapping information is the same as the number of bits of the low-order addresses.
6. The method according to claim 5, wherein at the exit of the final transmission channel of the current bus transaction, the low-order address carried by the current bus transaction is restored to the low-order address originally carried by the current bus transaction based on the mapping information and the first spatial mapping rule, and then the low-order address is sent to the corresponding slave device.
7. The method of claim 2, wherein upon the master initiating a bus transaction, the corresponding slave interleave access is completed by using the decoding space determined in the reference decoding space and each decoding space based on the second space mapping rule, comprising: determining a reference decoding space and a decoding space meeting the address step length in each decoding space as a currently used decoding space based on a second space mapping rule according to the address step length of the current bus transaction initiated by the main equipment; and transferring the current bus transaction to the currently used decoding space for decoding so as to send the current bus transaction to the corresponding slave device, thereby completing the access of the slave device.
8. An interconnection bus interleave access apparatus applied to a network-on-chip-based communication system including a network-on-chip and a plurality of master devices and a plurality of slave devices respectively connected to the network-on-chip, the apparatus comprising: a configuration module, configured to configure the network on chip by adding an auxiliary decoding space on the basis of a reference decoding space of the network on chip or adding a plurality of decoding spaces with different interleaving granularities from the reference decoding space; and the access module is used for completing interleave access of the corresponding slave device through the configured network-on-chip based on the space mapping rule when the master device initiates the bus transaction.
9. An electronic terminal comprising a memory, a processor and a computer program stored on the memory, characterized in that the processor executes the computer program to implement the method of any one of claims 1 to 7.
10. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the method of any of claims 1 to 7.

Description

Interconnection bus interleave access method, device, terminal and medium Technical Field The present application relates to the field of integrated circuit design technologies, and in particular, to an access method, an access device, a terminal, and a medium for an interconnection bus interleave. Background NOCs (Network on Chip) are bridges over which a plurality of master devices and a plurality of slave devices communicate with each other. The design of both the master and slave devices is fixed, so the upper limits of bus width and frequency are also fixed. The low-order interleave technique is required when a master with high bus bit width wishes to have non-inductive access to multiple slaves. That is, the master device will poll the slaves in sequence according to the address decoding of the bus burst. The precondition for sequential polling is that the addresses issued by the master device are consecutive. However, in AI applications, DMA (Direct Memory Access )/DTE (DATA TRANSFER ENGINE, data handling engine) on SoC (System on Chip) mostly issues addresses with stride, which causes a contention efficiency problem of interleave, resulting in bandwidth loss. Disclosure of Invention In view of the above-mentioned drawbacks of the prior art, the present application aims to provide an access method, device, terminal and medium for an interconnection bus interleave, which are used for solving the problem of low stride access efficiency under low-level interleaving at present. To achieve the above and other related objects, a first aspect of the present application provides an access method of an interconnection bus interleave, which is applied to a network-on-chip-based communication system, where the communication system includes a network-on-chip and a plurality of master devices and a plurality of slave devices respectively connected to the network-on-chip, the method includes configuring the network-on-chip by adding an auxiliary decoding space or adding a plurality of decoding spaces with different interleaving granularities from the reference decoding space on the basis of a reference decoding space of the network-on-chip, and completing interleave access of the corresponding slave devices through the configured network-on-chip based on a space mapping rule when a bus transaction is initiated by a master device. In some embodiments of the first aspect of the present application, the types of the spatial mapping rules include a first spatial mapping rule and a second spatial mapping rule, and when the master initiates a bus transaction, based on the spatial mapping rule, the interleave access of the corresponding slave device is completed through the configured network on chip, including, when the master initiates the bus transaction, based on the first spatial mapping rule, the interleave access of the corresponding slave device is completed through the reference decoding space with the assistance of the auxiliary decoding space, or, when the master initiates the bus transaction, the interleave access of the corresponding slave device is completed through the use decoding space determined in the reference decoding space and each decoding space based on the second spatial mapping rule. In some embodiments of the first aspect of the present application, when a master initiates a bus transaction, the master completes interleave access of a corresponding slave device through a reference decoding space based on a first space mapping rule and with the assistance of an auxiliary decoding space, including determining, when the master initiates a current bus transaction, a transmission channel initially allocated to the current bus transaction in an on-chip network based on a low-order address carried by the current bus transaction according to an interleaving granularity of the reference decoding space, determining whether the transmission channel initially allocated to the current bus transaction is consistent with a final transmission channel of a last bus transaction, if not, mapping the current bus transaction to the corresponding auxiliary decoding space based on the first space mapping rule to decode to determine the final transmission channel of the current bus transaction in the on-chip network, if so, determining the transmission channel initially allocated to the current bus transaction as the final transmission channel of the current bus transaction, and sending the current bus transaction to the corresponding slave device through the final transmission channel of the current bus transaction to complete the slave device access. In some embodiments of the first aspect of the present application, the mapping of the current bus transaction onto the corresponding auxiliary decoding space based on the first spatial mapping rule includes generating a corresponding mapped low-order address based on the first spatial mapping rule, the low-order address carried by the current bus transaction, and the h