CN-122027406-A - Digital baseband communication receiving link circuit and data receiving method

CN122027406ACN 122027406 ACN122027406 ACN 122027406ACN-122027406-A

Abstract

The invention discloses a digital baseband communication receiving link circuit and a data receiving method, which relate to the technical field of data communication, wherein the circuit comprises a down-sampling module, a code element integer module, a code element synchronous module, a decoding module and a CRC (cyclic redundancy check) module; the down-sampling module comprises a CIC down-sampling circuit and a half-band filter down-sampling circuit, the code element integer module comprises a delay circuit, a level comparison circuit and a level turning circuit, the code element synchronous module comprises an interpolator circuit, an error detection circuit, a loop filter, a numerical control oscillator and a sampling judgment circuit, the decoding module comprises a decoding state machine circuit and a data judgment circuit, and the CRC check module comprises a CRC mode control circuit, a CRC-5 check circuit and a CRC-16 check circuit. The invention reduces the inter-code crosstalk and error rate caused by the synchronous error, thereby improving the accuracy of the received data and the signal-to-noise ratio tolerance on the whole.

Inventors

WU YUCHAO
Chen Zhankang
WANG DEMING

Assignees

华南师范大学

Dates

Publication Date: 20260512
Application Date: 20260302

Claims (10)

1. The digital baseband communication receiving link circuit is characterized by comprising a downsampling module, a code element shaping module, a code element synchronization module, a decoding module and a Cyclic Redundancy Check (CRC) module, wherein the code element shaping module is respectively connected with the downsampling module and the code element synchronization module, and the decoding module is respectively connected with the code element synchronization module and the CRC module; The down-sampling module comprises a cascade integration comb CIC down-sampling circuit and a half-band filter down-sampling circuit, and the CIC down-sampling circuit is connected with the half-band filter down-sampling circuit; The code element shaping module comprises a delay circuit, a level comparison circuit and a level turning circuit, wherein the level comparison circuit is respectively connected with the delay circuit and the level turning circuit; The code element synchronization module comprises an interpolator circuit, an error detection circuit, a loop filter, a numerical control oscillator and a sampling decision circuit, wherein the interpolator circuit is respectively connected with the numerical control oscillator and the error detection circuit, and the loop filter is respectively connected with the error detection circuit, the sampling decision circuit and the numerical control oscillator; The decoding module comprises a decoding state machine circuit and a data judging circuit, and the decoding state machine circuit is connected with the data judging circuit; The CRC module comprises a CRC mode control circuit, a CRC-5 check circuit and a CRC-16 check circuit, and the CRC mode control circuit is respectively connected with the CRC-5 check circuit and the CRC-16 check circuit.
2. The digital baseband communication receive link circuit of claim 1, wherein the CIC down-sampling circuit comprises a multi-stage integrator circuit and a multi-stage comb filter circuit, the multi-stage integrator circuit and the multi-stage comb filter circuit being connected, the half-band filter down-sampling circuit comprising a plurality of delay registers, multipliers, and adders, the multipliers being connected to the delay registers and the adders, respectively.
3. A data receiving method, characterized in that the data receiving method is implemented based on the digital baseband communication receiving link circuit according to any one of claims 1 to 2, the data receiving method comprising: Performing downsampling processing on the received target data with different rates based on the downsampling module to obtain the downsampled target data; Performing delay processing on the target data subjected to the downsampling processing based on the delay circuit to obtain target data subjected to the delay processing, and performing level consistency comparison on the target data subjected to the delay processing based on the level comparison circuit to obtain a level consistency comparison result; Performing level inversion processing on the target data after delay processing by using the level consistency comparison result based on a level inversion circuit to obtain the target data after level inversion processing; performing time sequence synchronization processing on the target data subjected to the level overturning processing based on the code element synchronization module to obtain the target data subjected to the time sequence synchronization processing, and determining a synchronous clock signal; the decoding module decodes the target data subjected to the time sequence synchronization processing based on the synchronous clock signal to obtain decoded data; And performing cyclic redundancy check on the decoded data based on the CRC check module to obtain a cyclic redundancy check result, and determining the received target data based on the cyclic redundancy check result.
4. The method according to claim 1, wherein the downsampling module downsamples the received target data at different rates to obtain downsampled target data, comprising: performing 5 times of downsampling processing on the target data based on a CIC downsampling circuit in a downsampling module to obtain target data subjected to 5 times of downsampling processing; and performing 2 times of downsampling processing on the target data subjected to 5 times of downsampling processing based on a half-band filter downsampling circuit in the downsampling module to obtain the target data subjected to downsampling processing.
5. The data receiving method according to claim 1, wherein the delay processing is performed on the down-sampled target data based on the delay circuit to obtain the delayed target data, and the level coincidence comparison is performed on the delayed target data based on the level comparison circuit to obtain the level coincidence comparison result, comprising: Performing delay processing of a preset code element length on the target data after the down-sampling processing based on a delay circuit to obtain target data after the delay processing; and determining a first level of the target data after delay processing and a second level of the target data after downsampling processing, and carrying out level coincidence comparison on the first level and the second level based on a level comparison circuit to obtain a level coincidence comparison result.
6. The data receiving method according to claim 1, wherein the symbol-based synchronization module performs timing synchronization processing on the level-flipped target data, obtains the timing-synchronized target data, and determines a synchronization clock signal, comprising: synchronizing the target data subjected to the level inversion processing with a local time sequence based on a code element synchronization module to obtain target data subjected to the time sequence synchronization processing; performing multistage register delay on the target data subjected to the level inversion processing based on an interpolator circuit to obtain multistage output data, and constructing a first base function, a second base function and a third base function based on the multistage output data; Determining an interpolation interval based on a numerical control oscillator, multiplying the interpolation interval with a first base function to obtain a first coefficient, and multiplying the interpolation interval with a second base function to obtain a second coefficient; Performing two-stage register delay processing on the interpolation interval to obtain an interpolation interval after the two-stage register delay processing, and determining a third coefficient based on the interpolation interval after the two-stage register delay processing and the first coefficient; determining an interpolation output based on the third coefficient, the second coefficient, and a third basis function; the error detection circuit carries out register processing on the interpolation output based on a two-stage register to obtain a first sampling point and a second sampling point, and determines error data based on the interpolation output, the first sampling point and the second sampling point; The loop filter outputs a digital control word based on the error data, calculates a new interpolation interval based on the digital control word, and determines a synchronous clock signal based on the new interpolation interval.
7. The data receiving method according to claim 6, wherein the expression of the first coefficient is: , Wherein, the For the first coefficient, f1 is the first basis function, uk is the interpolation interval; the expression of the second coefficient is: , Wherein, the For the second coefficient, f2 is the second basis function, uk is the interpolation interval; the expression of the third coefficient is: , Wherein, the As a result of the third coefficient being the value of, As a result of the first coefficient of the coefficient, Interpolation interval after delay processing of the two-stage register; the expression of the interpolation output is: , Wherein, the For the interpolation output it is possible, As a result of the third coefficient being the value of, For the second coefficient, f3 is the third basis function.
8. The data receiving method according to claim 6, wherein the expression of the error data is: , Wherein, the As the data of the errors it is, As a first sampling point of the sample, For the interpolation output it is possible, Is the second sampling point.
9. The data receiving method according to claim 1, wherein the decoding module performs decoding processing on the target data after the timing synchronization processing based on the synchronization clock signal to obtain decoded data, comprising: Determining decoding operation information and state jump information of the target data after time sequence synchronization processing by using a synchronous clock signal based on a decoding state machine of the decoding module; and decoding the target data subjected to time sequence synchronization processing by using the decoding operation information and the state jump information based on the data judging circuit to obtain decoded data.
10. The method according to claim 1, wherein the performing cyclic redundancy check on the decoded data based on the CRC check module to obtain a cyclic redundancy check result includes: a CRC mode control circuit of the CRC check module generates a CRC mode selection signal based on the decoded data; And determining a selection result of the CRC-5 checking circuit and the CRC-16 checking circuit based on the mode selection signal, and performing cyclic redundancy check on the decoded data based on the selection result to obtain a cyclic redundancy check result.

Description

Digital baseband communication receiving link circuit and data receiving method Technical Field The present invention relates to the field of data communication technologies, and in particular, to a digital baseband communication receiving link circuit and a data receiving method. Background In the field of internet of things, an ultrahigh frequency wireless communication technology is used as a long-distance communication means, and is widely applied to scenes such as article identification, tracking, positioning and management, and most of the existing ultrahigh frequency wireless communication chips are usually designed to be optimized for specific communication rates. However, in practical application, when the tag returns data in a back scattering manner, since the rate is determined by multiple transmission rates of the ultrahigh frequency wireless communication chip, there is a significant difference in the data rate returned by the tag, and a multiple application environment in which multiple fixed rates coexist is formed. The existing ultrahigh frequency wireless communication chip has a certain implementation difficulty in the aspect of processing the multi-rate data stream, and a solidified hardware circuit of the existing ultrahigh frequency wireless communication chip is difficult to realize for data receiving and processing. Therefore, how to configure the receive link hardware circuitry to accommodate the reception of multiple rate data is a hotspot and difficulty of current designs. In addition, since there is a deviation in the data rate returned by the tag, the uhf wireless communication chip cannot decode the data returned by the tag at fixed time intervals. This requires that the uhf wireless communication chip accurately recover the clock information from the tag-returned digital baseband data stream, which does not contain an independent clock signal, to determine the start and end boundaries of each symbol. However, the conventional synchronization method based on the phase-locked loop or the delay phase-locked loop is effective under certain conditions, but has the problems of weak anti-interference capability and incapability of well coping with phase jump in encoding, so that the signal-to-noise ratio margin of decoding is reduced. Disclosure of Invention The invention aims to overcome the defects of the prior art, and provides a digital baseband communication receiving link circuit and a data receiving method, which reduce inter-code crosstalk and error rate caused by synchronous errors, thereby improving the accuracy of received data and the signal-to-noise ratio tolerance on the whole. In order to solve the technical problems, the invention provides a digital baseband communication receiving link circuit, which comprises a down-sampling module, a code element shaping module, a code element synchronization module, a decoding module and a Cyclic Redundancy Check (CRC) module, wherein the code element shaping module is respectively connected with the down-sampling module and the code element synchronization module, and the decoding module is respectively connected with the code element synchronization module and the CRC module; The down-sampling module comprises a cascade integration comb CIC down-sampling circuit and a half-band filter down-sampling circuit, and the CIC down-sampling circuit is connected with the half-band filter down-sampling circuit; The code element shaping module comprises a delay circuit, a level comparison circuit and a level turning circuit, wherein the level comparison circuit is respectively connected with the delay circuit and the level turning circuit; The code element synchronization module comprises an interpolator circuit, an error detection circuit, a loop filter, a numerical control oscillator and a sampling decision circuit, wherein the interpolator circuit is respectively connected with the numerical control oscillator and the error detection circuit, and the loop filter is respectively connected with the error detection circuit, the sampling decision circuit and the numerical control oscillator; The decoding module comprises a decoding state machine circuit and a data judging circuit, and the decoding state machine circuit is connected with the data judging circuit; The CRC module comprises a CRC mode control circuit, a CRC-5 check circuit and a CRC-16 check circuit, and the CRC mode control circuit is respectively connected with the CRC-5 check circuit and the CRC-16 check circuit. Optionally, the CIC downsampling circuit includes a multi-stage integrating circuit and a multi-stage comb filter circuit, the multi-stage integrating circuit is connected with the multi-stage comb filter circuit, the half-band filter downsampling circuit includes a plurality of delay registers, multipliers and adders, and the multipliers are respectively connected with the delay registers and the adders. In addition, the invention also provides a data receiving meth