CN-122027444-A - Method and system for monitoring data flow of loop test module

CN122027444ACN 122027444 ACN122027444 ACN 122027444ACN-122027444-A

Abstract

The application discloses a data flow monitoring method and system for a loop test module, and belongs to the technical field of computers. The method comprises the steps of intercepting an original data stream at a loop transmitting end bypass, generating a transmitting end characteristic fingerprint with a fixed length, associating the transmitting end characteristic fingerprint with a transmitting clock label, then writing the transmitting end characteristic fingerprint into an asynchronous ring buffer area in sequence, intercepting the returning data stream at a loop receiving end bypass, generating a receiving end characteristic fingerprint by adopting the same algorithm, capturing a receiving clock label, determining a sliding window range by a matching engine based on the receiving clock label and a preset time delay parameter, parallelly reading a plurality of transmitting end characteristic fingerprints in the window, screening according to time deviation, comparing the transmitting end characteristic fingerprints with the receiving end characteristic fingerprint, judging to be normal if the transmitting end characteristic fingerprint is matched, and starting an abnormal processing flow if the transmitting end characteristic fingerprint is matched. The application realizes low resource cost, non-invasive and high real-time data stream monitoring through the characteristic fingerprint compression storage and the parallel matching mechanism of the asynchronous ring buffer and the sliding window, and effectively adapts to the high-speed loop-back test scene.

Inventors

DONG XIN
ZENG XIANLONG
CHEN SHAN

Assignees

深圳万德溙光电科技有限公司

Dates

Publication Date: 20260512
Application Date: 20260314

Claims (10)

1. The method for monitoring the data flow of the loop test module is characterized by comprising the following steps of: At the loop transmitting end, intercepting an original data stream in real time through a hardware interface of bypass deployment, generating a transmitting end characteristic fingerprint with a fixed length by adopting a lightweight mapping algorithm, and writing the transmitting end characteristic fingerprint into an asynchronous annular buffer area in sequence after associating the transmitting end characteristic fingerprint with a corresponding transmitting clock label; at the loop receiving end, the returned data stream returned from the tested loop module is intercepted in real time through a hardware interface of bypass deployment, the characteristic fingerprint of the receiving end is generated by adopting the light-weight mapping algorithm which is the same as that of the transmitting end, and the receiving clock label when the returned data stream arrives is captured; The matching engine determines a sliding window range in the asynchronous ring buffer based on the receiving clock label and a preset loop path delay parameter; The matching engine reads a plurality of characteristic fingerprints of the transmitting end and corresponding transmitting clock labels in the sliding window range from the asynchronous ring buffer in parallel; According to whether the time deviation of the sending clock label and the receiving clock label is in a preset time delay jitter range, validity screening is carried out on a plurality of sending end characteristic fingerprints read in parallel, and the screened valid sending end characteristic fingerprints are compared with receiving end characteristic fingerprints; If the matched fingerprint exists, the data transmission is judged to be normal, and if the matched fingerprint does not exist, an abnormal processing flow is started.
2. The method of claim 1, wherein the predetermined loop path delay parameters include a nominal delay and a delay jitter range, wherein the matching engine determines a sliding window range in the asynchronous ring buffer based on the receive clock tag and the predetermined loop path delay parameters, and wherein the method comprises: subtracting nominal delay from the receiving clock label by the matching engine to obtain center reference time; The time delay jitter range and the average arrival interval of the system data packets determine the width of a sliding window; Wherein the depth N of the asynchronous ring buffer is based on the maximum physical delay of the loop path System packet average inter-arrival And a safety margin M configured to satisfy The safety margin M is determined based on the jitter standard deviation of the loop-back path and the desired confidence coefficient.
3. The method of claim 2, further comprising the step of adaptively adjusting a range of delay jitter: the matching engine monitors the records filtered by the deviation of the sending clock label and the center reference time exceeding the current time delay jitter range; If the filtered record exists and the matching is successful after the delay jitter range is enlarged in the subsequent abnormal processing flow, recording a filtering-success event; When the number of times of continuous occurrence of the filtering-success event reaches a preset threshold value, the time delay jitter range is increased according to a preset stepping value.
4. The method of claim 3, wherein the step of adaptively adjusting the range of delay jitter further comprises: When the recorded event is not filtered due to exceeding the delay jitter range within a preset time period or after processing a preset number of data packets, the delay jitter range is gradually reduced until the delay jitter range is restored to a preset initial value or a new filtering event is detected.
5. The method of claim 1, wherein the write operation of the asynchronous ring buffer is driven by a sender clock domain and the read operation is driven by a receiver clock domain, the method further comprising the step of synchronizing pointers across the clock domains: after updating the write pointer each time, the transmitting end converts the binary value of the write pointer into Gray code and transmits the Gray code to the receiving end clock domain through the two-stage synchronous register; The receiving end decodes the synchronous Gray code into binary system and compares with the local read pointer to judge the empty/full state of the buffer area and ensure the accuracy of the reading operation.
6. The method of claim 5, wherein the write pointer and the read pointer are added with a wrap-around flag bit at the high position, the wrap-around flag bit is turned over every time the pointer wraps around, the transmitting end transfers the complete pointer value containing the wrap-around flag bit across clock domains after converting the complete pointer value into Gray codes, and the receiving end judges the empty/full state of the buffer area based on the complete pointer value containing the wrap-around flag bit after decoding.
7. The method according to claim 1, wherein the matching engine reads in parallel a plurality of sender characteristic fingerprints and their corresponding sender clock labels within a sliding window from the asynchronous ring buffer, and specifically comprises: the asynchronous ring buffer adopts a multi-port memory structure, and the matching engine reads all recording units corresponding to a plurality of addresses in the sliding window in parallel through a plurality of reading ports in one clock period, wherein each recording unit comprises a sending clock label and associated sending end characteristic fingerprints; All the record units read out in parallel are sent to a group of parallel comparator arrays for subsequent validity screening and fingerprint comparison.
8. The method of claim 1, wherein initiating an exception handling flow comprises: if no match exists in the primary comparison, judging whether a record filtered because the time deviation exceeds the time delay jitter range exists or not; If the characteristic fingerprints exist, the preset time delay jitter range is gradually enlarged, validity screening is conducted on all records in the sliding window again based on the same central reference time, and the characteristic fingerprints of the transmitting end which pass the screening are brought into the candidate set and are compared with the characteristic fingerprints of the receiving end again; If the time delay jitter range is expanded to the preset upper limit and is still not matched, or the filtered record is not present, the occurrence of data abnormality is finally judged.
9. The method of claim 8, wherein initiating an exception handling flow further comprises: Triggering an abnormal alarm signal and activating an abnormal log recording module when the occurrence of data abnormality is finally judged; The abnormal log record module assembles the related information of the current abnormality into a log entry with a fixed length and writes the log entry into the nonvolatile memory, wherein the log entry at least comprises a current receiving clock label, a receiving end characteristic fingerprint, a sending end characteristic fingerprint candidate set in a sliding window, a corresponding sending clock label, a matching failure reason code and a snapshot of a current system state register.
10. A loop test module data flow monitoring system applied to the loop test module data flow monitoring method of claims 1-9, comprising: the sending end monitoring unit is deployed at a bypass of a loop sending end data path and comprises: a first hardware interception interface for non-invasively intercepting the original data stream in real time; the transmitting end fingerprint generation module is used for generating a transmitting end characteristic fingerprint with fixed length from the original data stream by adopting a lightweight mapping algorithm; the asynchronous ring buffer is used for associating the characteristic fingerprint of the transmitting end with the synchronously captured transmitting clock label and then storing the characteristic fingerprint of the transmitting end in sequence; The receiving end monitoring unit is deployed at a bypass of a data path of a loop receiving end and comprises: The second hardware interception interface is used for non-invasively intercepting the return data flow returned from the tested loop module in real time; the receiving end fingerprint generation module is used for generating a receiving end characteristic fingerprint from the feedback data stream by adopting the same lightweight mapping algorithm as that of the transmitting end, and synchronously capturing a receiving clock label; the matching engine is respectively connected with the asynchronous ring buffer area and the receiving end monitoring unit and is used for: determining a sliding window range in an asynchronous ring buffer based on a receiving clock tag and a preset loop path delay parameter; A plurality of transmitting end characteristic fingerprints and corresponding transmitting clock labels in the sliding window range are read in parallel; according to the comparison result of the time deviation of the sending clock label and the receiving clock label and the preset time delay jitter range, validity screening is carried out on a plurality of sending end characteristic fingerprints read in parallel, and the screened valid sending end characteristic fingerprints are compared with receiving end characteristic fingerprints; If the matched fingerprint exists, the data transmission is judged to be normal, and if the matched fingerprint does not exist, an abnormal processing flow is started.

Description

Method and system for monitoring data flow of loop test module Technical Field The application belongs to the technical field of computers, and particularly relates to a data flow monitoring method and system for a loop test module. Background With the continued evolution of high-speed communication interfaces and system-on-chip (SoC) internal bus architectures, loop-back testing has become increasingly important as a key means of verifying data path integrity and transmission accuracy. In the chip-level or board-level function verification process, the loop test realizes the evaluation of core indexes such as the error rate, the time sequence stability, the protocol consistency and the like of the link by returning the data output by the transmitting end to the receiving end through the tested channel. The test mode is widely applied to high-speed SerDes, PCIe, DDR, noC and other high-bandwidth interconnection structures, and is a basic link for ensuring the reliable operation of the system. The traditional loop monitoring scheme generally adopts a full-volume data comparison mechanism, namely, a complete original transmitted data copy is cached at a receiving end and is checked with the returned data bit by bit. Although the method can ensure the detection precision, the method exposes a remarkable bottleneck when facing data streams with the speed of hundreds of Gbps and above. In the prior art, on one hand, a large amount of on-chip or on-board memory resources are consumed because of the need of storing mass raw data, so that the area and cost constraint is difficult to meet, and on the other hand, high processing delay is introduced into complex real-time comparison logic, so that a monitoring system cannot synchronously track high-speed data flow, and missed detection or monitoring blind areas are easy to generate. In addition, such intrusive monitoring architectures typically occupy additional bus bandwidth and increase power consumption overhead, interfere with performance of the module under test under real workload, and reduce the effectiveness of test results. Therefore, there is a need for a low-resource-overhead, non-invasive and highly time-efficient loop test data flow monitoring method that combines detection accuracy with system transparency. Disclosure of Invention The invention aims to provide a method and a system for monitoring a data stream of a loop test module, which can effectively solve the problems in the background technology. In order to achieve the above purpose, the technical scheme adopted by the invention is as follows: in a first aspect, the present application discloses a method for monitoring a data stream of a loop test module, including: At the loop transmitting end, intercepting an original data stream in real time through a hardware interface of bypass deployment, generating a transmitting end characteristic fingerprint with a fixed length by adopting a lightweight mapping algorithm, and writing the transmitting end characteristic fingerprint into an asynchronous annular buffer area in sequence after associating the transmitting end characteristic fingerprint with a corresponding transmitting clock label; at the loop receiving end, the returned data stream returned from the tested loop module is intercepted in real time through a hardware interface of bypass deployment, the characteristic fingerprint of the receiving end is generated by adopting the light-weight mapping algorithm which is the same as that of the transmitting end, and the receiving clock label when the returned data stream arrives is captured; The matching engine determines a sliding window range in the asynchronous ring buffer based on the receiving clock label and a preset loop path delay parameter; The matching engine reads a plurality of characteristic fingerprints of the transmitting end and corresponding transmitting clock labels in the sliding window range from the asynchronous ring buffer in parallel; According to whether the time deviation of the sending clock label and the receiving clock label is in a preset time delay jitter range, validity screening is carried out on a plurality of sending end characteristic fingerprints read in parallel, and the screened valid sending end characteristic fingerprints are compared with receiving end characteristic fingerprints; If the matched fingerprint exists, the data transmission is judged to be normal, and if the matched fingerprint does not exist, an abnormal processing flow is started. Further, the method further comprises the step of adaptively adjusting the delay jitter range: the matching engine monitors the records filtered by the deviation of the sending clock label and the center reference time exceeding the current time delay jitter range; If the filtered record exists and the matching is successful after the delay jitter range is enlarged in the subsequent abnormal processing flow, recording a filtering-success event; When the number of time