CN-122027575-A - Signal processing module and system

Abstract

The embodiment of the invention discloses a signal processing module and a system, wherein the signal processing system comprises an interface unit used for carrying out data exchange with external equipment, a main control unit connected with the interface unit and used for configuring a data transmission interval, the main control unit sequentially caches received data in time slices according to the data transmission interval and sends the data to the data processing unit after one time slice of data is cached each time, the data transmission interval is larger than the sum of the calculation time of the data processing unit for each time slice of data and the data carrying time, the data processing unit comprises a plurality of calculation subunits used for decomposing the current calculation task into a plurality of subtasks after receiving the data sent by the main control unit, carrying out parallel processing on the subtasks through the calculation subunits, and outputting the processing result to the external equipment through the main control unit and the interface unit. By adopting the technical scheme, the real-time performance of data transmission is improved.

Inventors

• WU JUN

Assignees

• 北京忆元科技有限公司

Dates

Publication Date

20260512

Application Date

20260224

Priority Date

20251205

Claims (10)

1. 1. A signal processing module, comprising: The interface unit is used for being connected with the external equipment to receive data sent by the external equipment and output the data in the current information processing module to the external equipment; The main control unit is connected with the interface unit and is used for configuring a data transmission interval, the data transmission interval is used for dividing a current data stream to be transmitted, which is continuously input, into continuous time slice data for transmission, the main control unit sequentially caches the received data according to the data transmission interval by taking time slices as units, and the received data is sent to the data processing unit after one time slice data is cached each time, wherein the data transmission interval is larger than the sum of the calculation time consumption and the data carrying time consumption of each time slice data by the data processing unit; the data processing unit is connected with the main control unit and used for executing parallel computing tasks after receiving the data sent by the main control unit and outputting the computing results to external equipment through the main control unit and the interface unit.
2. 2. The module according to claim 1, wherein the main control unit is specifically configured to: Calculating the calculation time consumption of the data processing unit for executing each calculation task according to the calculation amount corresponding to the current data to be transmitted, the calculation power of the data processing unit and the utilization rate of the data processing unit, wherein the calculation amount represents the number of times of mathematical operation; calculating the time consumption of data handling of each time slice of data stored by the data processing unit according to the bandwidth of the DMA in the data processing unit and the utilization rate of the DMA; Taking the sum of the calculated time consumption and the data carrying time consumption as the overall processing delay of the data processing unit; And setting a data transmission interval to be larger than the overall processing delay.
3. 3. The module of claim 1, wherein the signal processing module further comprises: The Field Programmable Gate Array (FPGA) is connected between the interface unit and the main control unit, and is used for sequentially caching the received current data to be transmitted by taking a time slice as a unit according to the data transmission interval, and sending a data caching completion signal to the main control unit after caching of one time slice data is completed each time; Correspondingly, the main control unit is specifically configured to: And after receiving the data caching completion signal each time, sending a data transmission instruction to the FPGA so as to instruct the FPGA to transmit the data cached in the FPGA to the memory of the main control unit according to the data transmission interval.
4. 4. The module of claim 3, wherein the FPGA is configured with a first direct memory access DMA controller, and the master control unit is configured to: And triggering a first DMA controller after receiving the data caching completion signal each time so as to control the first DMA controller to transmit the data cached in the FPGA to the memory of the main control unit for caching according to the data transmission interval.
5. 5. The module according to claim 1, wherein the data processing unit is configured with a second DMA controller, and the main control unit is configured to: and triggering the second DMA controller after one time slice data is cached each time, so as to transmit the time slice data cached in the memory of the main control unit to the memory of the data processing unit through the second DMA controller.
6. 6. The module according to claim 1, wherein the main control unit is specifically configured to: and triggering a second DMA controller after receiving a calculation task completion signal sent by the data processing unit, so as to transmit a calculation result to the memory of the main control unit through the second DMA controller, and transmitting the calculation result from the memory of the main control unit to the FPGA to output data.
7. 7. The module of claim 4, wherein the first DMA controller is configured with a plurality of channels, and wherein the master control unit is configured to: Dynamically allocating the priority of the DMA channel according to the data type; and triggering the first DMA controller to transmit data according to the order of the priority from high to low.
8. 8. The module of claim 1, wherein the interface unit comprises: And the high-speed connector and the low-speed universal asynchronous receiver are connected with the main control unit.
9. 9. The module of claim 2, wherein the interface unit comprises: The high-speed connector is connected with the FPGA and used for transmitting high-speed signals; And the low-speed universal asynchronous receiver-transmitter is connected with the main control unit and is used for transmitting low-speed signals.
10. 10. A signal processing system comprising a signal receiving apparatus and a signal processing module as claimed in any one of claims 1 to 9, wherein, The signal processing module is installed on the signal receiving equipment in a pluggable mode.

Description

Signal processing module and system Technical Field The embodiment of the invention relates to the technical field of wireless communication signal processing, in particular to a signal processing module and a system. Background In modern communication technology, long wave, medium wave and short wave communication are widely applied to the fields of military, navigation, emergency communication and the like, and extremely high requirements are provided for the instantaneity, accuracy and stability of signal processing. Therefore, how to efficiently process multi-channel signals and realize low-delay signal transmission and analysis becomes a key problem to be solved in the field. In long-wave, medium-wave and short-wave communication systems, signal transmission is extremely susceptible to interference from complex environmental factors, such as multipath fading, doppler shift and frequency hopping communication modes, which place extremely stringent demands on the real-time processing capability of signals. Multipath fading is the process of making signals reach a receiving end through a plurality of paths with different lengths in the propagation process, and the signals of the paths interfere with each other, so that the amplitude and the phase of the received signals are randomly changed. For example, in mountain areas or environments where urban high buildings stand up, short wave signals can reflect between mountain peaks and buildings for multiple times, so that multipath effects are generated, and the communication quality is seriously affected. The doppler shift is the difference between the frequency of the wave received by the receiving body and the frequency transmitted by the transmitting source when there is relative motion between the transmitting source and the receiving body. In a scene of high-speed movement, such as an airplane, a high-speed rail, etc., the frequency shift phenomenon can cause signal distortion, and the difficulty of signal processing is increased. The frequency hopping communication mode is that the radio frequency frequencies of both communication parties are in pseudo-random and synchronous hopping in the form of discrete frequency in the appointed frequency table, so as to improve the anti-interference capability and confidentiality of communication, but the real-time and synchronism of signal processing are also in higher requirement. In the conventional signal processing scheme, a CPU and/or an FPGA are/is mostly adopted to perform data calculation, however, the single-core processing capability of the CPU is limited, and for complex algorithms such as matrix operation, multiple data handling is required. In processing multi-channel signals, large amounts of data need to be transferred frequently between the CPU, memory and other processing units, which not only consumes a lot of time, but also increases the power consumption of the system. In addition, due to the limited resource size and development complexity of FPGAs, traditional FPGA architectures increasingly expose bottlenecks in terms of logic resource utilization, power consumption control, and development cycles as the number of signal channels increases to thousands or even tens of thousands of ways. Because the FPGA has limited calculation power, the aim of multichannel real-time processing can be achieved only by increasing the number of the FPGAs, but the problem is that the whole equipment is increased and the power consumption is greatly improved. Meanwhile, the processing efficiency of the FPGA on the computationally intensive tasks such as complex filtering, demodulation, equalization and the like is limited, and the requirements of large-scale parallel signal processing and instantaneity are difficult to fully meet. Therefore, in the traditional signal processing scheme, when the signal is processed in multiple channels, the operation efficiency is low, the time delay is higher, the real-time performance is not up to the standard, and certain limitations exist in the aspects of performance expansion and flexibility. Disclosure of Invention The embodiment of the invention provides a signal processing module and a system, which improve the real-time performance of data transmission. In a first aspect, the present invention provides a signal processing module, including: The interface unit is used for being connected with the external equipment to receive data sent by the external equipment and output the data in the current information processing module to the external equipment; The main control unit is connected with the interface unit and is used for configuring a data transmission interval, the data transmission interval is used for dividing a current data stream to be transmitted, which is continuously input, into continuous time slice data for transmission, the main control unit sequentially caches the received data according to the data transmission interval by taking time slices as units, a