CN-122027585-A - Programmable network interconnection core, network interconnection unit and multi-core interconnection structure

CN122027585ACN 122027585 ACN122027585 ACN 122027585ACN-122027585-A

Abstract

The invention discloses a programmable network interconnection core particle, a network interconnection unit and a multi-core particle interconnection structure. The network interconnection core particle comprises a control core, a plurality of processing cores and a plurality of routing nodes corresponding to the processing cores, wherein each processing core is provided with an external interface and a network interface, each network interface is connected with the corresponding routing node through two-way communication, the routing nodes are actually arranged or virtually arranged into a matrix with a plurality of rows and a plurality of columns, adjacent routing nodes in the same row and the same column are respectively connected through two-way communication so as to connect all the processing cores together to form an information interconnection network channel, and the control core is connected with each routing node, monitors the state of the control core and controls the transmission direction of the switching routing node. The invention can freely program and adjust the communication paths among different interfaces, and has high interconnection flexibility and convenient maintenance.

Inventors

TAN LINGYUN
CHEN ZHENGSHENG
LUO YONG
JI XINWEI

Assignees

遇贤微电子(广州)有限公司

Dates

Publication Date: 20260512
Application Date: 20260317

Claims (10)

1. The programmable network interconnection core particle is characterized by comprising a control core, a plurality of processing cores and a plurality of routing nodes corresponding to the processing cores, wherein each processing core is provided with an external interface and a network interface, the network interface of each processing core is in communication connection with the corresponding routing node through a bidirectional passage, the routing nodes are actually arranged or virtually arranged into a matrix with a plurality of rows and a plurality of columns, the adjacent routing nodes in the same row are connected together through the bidirectional passage, the adjacent routing nodes in the same column are connected together through the bidirectional passage, and the network interfaces of all the processing cores are connected together through the routing nodes to form an information interconnection network channel; the control core is connected with each routing node, monitors the state of each routing node and controls the switching of the transmission direction of the routing node.
2. The programmable network interconnect die of claim 1 wherein said processing core is a unit that processes signals received or transmitted by said external interface.
3. The programmable network interconnect die of claim 2 wherein said processing core isolates, encrypts or filters signals received or transmitted by said external interface.
4. The programmable network interconnect die of claim 1 wherein said external interface is a standardized interface.
5. The programmable network interconnect die of claim 4 wherein the external interface is UCIe interface, a BoW interface, or an AIB interface.
6. A network interconnection unit is characterized by comprising a network interconnection core particle, a memory and an operation instruction, wherein the network interconnection core particle is a programmable network interconnection core particle according to any one of claims 1-5, the operation instruction is stored in the memory, the control core executes the operation instruction to determine an information transmission path and switch a fault path, the information transmission path in an information interconnection network channel is determined according to a preset data path optimization algorithm to control the communication direction of a routing node, whether the information transmission path is faulty or not is judged according to the state of the routing node, and when the information transmission path is faulty, the transmission direction of the routing node is adjusted according to a preset routing algorithm to switch the faulty information transmission path.
7. The network interconnection unit of claim 6, wherein when the control core controls the communication direction of the routing node according to a preset data path optimization algorithm, the control core determines the unit time information traffic of the routing node according to the state of the routing node and the current information transmission path, and optimizes the information transmission path according to the information traffic so as to avoid the unit time information traffic of the routing node being excessively large.
8. A multi-core interconnection structure is characterized by comprising a network interconnection unit, a packaging substrate and functional cores, wherein the network interconnection unit is the network interconnection unit according to claim 6, the network interconnection cores of the network interconnection unit are integrated in or mounted on the packaging substrate, and a plurality of the functional cores are mounted on or on the packaging substrate and electrically connected with the network interconnection cores.
9. The multi-die interconnect structure of claim 8, wherein the functional die is mounted on the package substrate and electrically connected to the network interconnect die via a trace on the package substrate or the functional die is mounted on the network interconnect die and electrically connected to the network interconnect die via a trace between the network interconnect die and the functional die.
10. The multi-pellet interconnect structure of claim 8 wherein said functional pellets comprise one or more of CPU, GPU, AI accelerators.

Description

Programmable network interconnection core, network interconnection unit and multi-core interconnection structure Technical Field The invention relates to the field of semiconductors and communication, in particular to a network interconnection core particle structure for multi-core particle interconnection, a network interconnection unit formed by the same and a multi-core particle interconnection structure. Background As moore's law slows down, the rise in single chip integration faces physical limits and cost bottlenecks. The multi-Die (Chiplet) technology has become an important direction for continued power growth by integrating Die (Die) of different functions into the same package. Heterogeneous multi-chip combines different process nodes and cores (such as CPU, GPU, AI accelerator, storage unit and the like) with different structures, and realizes high performance, low power consumption and flexible expansion through advanced packaging (such as 2.5D/3D) and high-efficiency interconnection. The existing heterogeneous core interconnection technology has the defects of poor interconnection flexibility, and incapability of adapting to diversified communication requirements of heterogeneous cores due to fixed NOC (Network-on-Chip) protocol. The maintainability is low, the whole package is required to be redesigned when the core particle is damaged or upgraded, and the cost is high. Therefore, there is an urgent need for a multi-die interconnect structure that can solve the above-mentioned problems. Disclosure of Invention The invention aims to provide a programmable network interconnection core particle, a network interconnection unit and a multi-core particle interconnection structure, which can freely program and adjust communication paths among different interfaces, and have high interconnection flexibility and convenient maintenance. In order to achieve the above purpose, the invention provides a programmable network interconnection core, comprising a control core, a plurality of processing cores and a plurality of routing nodes corresponding to the processing cores, wherein each processing core is provided with an external interface and a network interface, the network interface of each processing core is in communication connection with the corresponding routing node through a bidirectional passage, the routing nodes are actually arranged or virtually arranged into a matrix with a plurality of rows and columns, the adjacent routing nodes in the same row are connected together through the bidirectional passage, the adjacent routing nodes in the same column are connected together through the bidirectional passage, so that the network interfaces of all the processing cores are connected together through the routing nodes to form an information interconnection network channel, and the control core is connected with each routing node, monitors the state of each routing node and controls the transmission direction of the routing node to be switched. Compared with the prior art, in the network interconnection core particle, a plurality of processing cores with external interfaces are connected into a grid-shaped information interconnection network channel through a plurality of routing nodes, so that a plurality of interconnection lines are arranged between any two processing cores, each routing node is connected with at least three other routing nodes, and when a line between any two routing nodes fails, the processing cores can be switched and connected through other plurality of redundant lines, so that the network interconnection core particle has high flexibility, can switch the transmission path of the failure through the control of the control core, and is convenient to maintain. Furthermore, the invention can freely program and adjust the communication paths between different external interfaces in the network interconnection core by loading different programs on the control core. Preferably, the processing core is a unit for processing signals received or sent by the external interface. Specifically, the processing checks the signals received or sent by the external interface to perform isolation, encryption or filtering processing. Preferably, the external interface is a standardized interface. Specifically, the external interface is UCIe interface, boW interface or AIB interface. The scheme ensures that the invention adopts a general interconnection protocol, avoids the repeated design of network-on-chip for different computing units, and ensures that the network interconnection core particles can realize different topologies (such as 2D Mesh, torus, fat-Tree and the like) so as to adapt to the communication requirement of the multi-core particles. The invention also provides a network interconnection unit which comprises a network interconnection core particle, a memory and an operation instruction, wherein the network interconnection core particle is the programmable network interconnection co