CN-122027589-A - Protocol controller, test method, computing device and chip

Abstract

The application discloses a protocol controller, a testing method, computing equipment and a chip, and belongs to the technical field of chips. The protocol controller comprises an excitation generating module, a sending channel, an excitation response module and a receiving channel, wherein the excitation generating module is used for generating first test excitation and transmitting the first test excitation to the excitation response module through the sending channel, the excitation response module is used for obtaining first test response based on the first test excitation, transmitting the first test response to the excitation generating module through the receiving channel, and the excitation generating module is also used for checking whether the first test response is correct. The self-test flow provided by the application can be used for testing the CXL controller, and the asymmetric characteristic of the CXL controller is satisfied.

Inventors

• XU SHUAI
• PENG JIAXI

Assignees

• 海光信息技术股份有限公司

Dates

Publication Date

20260512

Application Date

20260202

Claims (20)

1. 1. A protocol controller, characterized in that the protocol controller comprises an excitation generating module, a transmitting path, an excitation responding module and a receiving path; the excitation generation module is used for generating a first test excitation, and transmitting the first test excitation to the excitation response module through the transmission path; the excitation response module is used for obtaining a first test response based on the first test excitation, and transmitting the first test response to the excitation generation module through the receiving channel; the stimulus generation module is further configured to verify whether the first test response is correct.
2. 2. The protocol controller according to claim 1, wherein the excitation generation module comprises a first mode selection unit and an excitation generation unit; the first mode selection unit is used for selecting a first functional mode; The stimulus generating unit is used for generating the first test stimulus according to the first functional mode.
3. 3. The protocol controller according to claim 2, wherein the stimulus generation module further comprises a first monitoring unit and a first verification unit; the first monitoring unit is used for monitoring an input interface of the excitation generation module and acquiring the first test response; the first verification unit is used for obtaining the first functional mode and verifying whether the first test response is corresponding to the first functional mode and the first test excitation.
4. 4. The protocol controller according to claim 1, wherein the stimulus response module comprises a second monitoring unit and a second verification unit; The second monitoring unit is used for monitoring an input interface of the excitation response module and acquiring the first test excitation; the second verification unit is used for obtaining a first functional mode and verifying whether the first test excitation is the excitation corresponding to the first functional mode.
5. 5. The protocol controller according to claim 4, wherein the stimulus response module further comprises a second mode selection unit and a response generation unit; The second mode selection unit is used for selecting the first functional mode; the response generation unit is configured to generate the first test response according to the first functional mode and the first test stimulus.
6. 6. The protocol controller according to any one of claims 1 to 5, further comprising at least one of a first selection unit, a second selection unit, and a third selection unit; the first selecting unit is used for switching the input of the sending channel from the upstream of the protocol controller or from the excitation generating module through a back pressure cutoff operation; The second selecting unit is used for switching the output of the sending channel to be sent to the downstream of the protocol controller or the excitation response module through the back pressure cut-off operation, and is used for switching the input of the receiving channel to be sent from the downstream of the protocol controller or the excitation response module through the back pressure cut-off operation; The third selecting unit is configured to switch the output of the receiving channel to be sent to the upstream of the protocol controller or the excitation generating module through a back pressure cutoff operation.
7. 7. The protocol controller according to any one of claims 1 to 5, further comprising an error detection module; The error detection module is used for transmitting a start test instruction to the excitation generation module and the excitation response module under the condition that the transmission of the sending channel or the receiving channel is wrong, and the start test instruction is used for indicating the excitation generation module and the excitation response module to perform self-test.
8. 8. The protocol controller according to any one of claims 1 to 5, wherein the transmission path is configured based on a transaction layer transmission path and a link layer transmission path, the transaction layer transmission path is configured to obtain a transaction layer packet by using a transaction layer format; The receiving path is formed based on a link layer receiving path and a transaction layer receiving path, the link layer receiving path is used for decapsulating the link layer message by adopting a link layer format, and the transaction layer receiving path is used for decapsulating the transaction layer message by adopting a transaction layer format.
9. 9. The protocol controller according to any one of claims 1 to 5, wherein the protocol controller is located on a switch, the switch further comprising a second protocol controller; The excitation generation module of the first protocol controller is used for generating a second test excitation, and transmitting the second test excitation to the second protocol controller through a transmission path of the first protocol controller; the receiving path and the sending path of the second protocol controller transmit the second test stimulus, and the second test stimulus is returned to the first protocol controller; the receiving path of the first protocol controller receives the second test stimulus and transmits the second test stimulus to the stimulus generation module of the first protocol controller; The stimulus generation module of the first protocol controller verifies that the received second test stimulus is a second test stimulus sent by itself.
10. 10. The protocol controller of claim 9, wherein the transmit path of the first protocol controller is configured by the central processor to be in a switch upstream port mode and the receive path of the first protocol controller is configured by the central processor to be in a switch downstream port mode; The transmit path of the second protocol controller is configured by the central processor to be in a switch downstream port mode, and the receive path of the second protocol controller is configured by the central processor to be in a switch upstream port mode.
11. 11. The protocol controller according to any one of claims 1 to 5, wherein, The protocol controller is used for executing a reset operation under the condition that the transmitted data error is detected; the stimulus generation module is used for generating the first test stimulus for self-test after the protocol controller executes the reset operation.
12. 12. The protocol controller of claim 11, wherein the protocol controller is a host responder port controller, wherein the transmit path comprises a transaction layer transmit path and a link layer transmit path; The transaction layer sending path is used for stopping transmitting the RWD to the link layer sending path and sending a retransmission request to a hardware network outside the protocol controller on the host when detecting that the RWD with the data request is in error; The protocol controller is used for resetting the transaction layer sending path under the condition that retransmission of a hardware network outside the protocol controller on the host fails; the receiving path is used for re-handshaking with the equipment at a protocol level; The protocol controller is further configured to send a retransmission request to a hardware network outside the protocol controller on the host after the self-test is completed; the receiving path is further configured to, after the self-test is completed, drain a packet generated during the test by responding to a retransmission request sent by the device.
13. 13. The protocol controller of claim 12, wherein the protocol controller is a host responder port controller, and wherein the receive path comprises a link layer receive path and a transaction layer receive path; The link layer receiving path is used for stopping transmitting the DRS to the transaction layer receiving path and sending a retransmission request to equipment when detecting that the DRS with data response is wrong; The protocol controller is configured to reset the link layer receiving path in case of retransmission failure of the device; the sending path is used for re-handshaking with a hardware network outside the protocol controller on the host at the protocol layer; the protocol controller is further configured to send a retransmission request to the device after the self-test is completed; The sending path is also used for responding to a retransmission request sent by a hardware network outside the protocol controller on the host after the self-test is finished, and draining the message generated during the test.
14. 14. The protocol controller according to any one of claims 1 to 5, wherein the protocol controller is an interface controller of an upstream device or an interface controller of a downstream device; the downstream device is configured to send a first request and a first credit card to the upstream device, where the first credit card carries a first identifier, and the first credit card is configured to instruct the downstream device to have an available storage space corresponding to the first identifier; the upstream device is configured to send a first packet corresponding to the first request to the downstream device; and the downstream equipment is used for storing the first message into an available storage space corresponding to the first identification code.
15. 15. The protocol controller according to claim 14, wherein, The upstream device is further configured to send a first type of credit to the downstream device via a credit channel after the first request is successfully consumed; and the downstream equipment is further used for releasing the available storage space corresponding to the first identification code under the condition that the first type of credit card is received, so that the first identification code can be multiplexed with other credit cards.
16. 16. The protocol controller according to claim 14, wherein, The upstream device is further configured to send a second type of credit to the downstream device through a credit channel when the first request is in error or the first message is in error; the downstream device is further configured to retransmit the first request to the upstream device if the second type of credit is received.
17. 17. The protocol controller according to claim 14, wherein, The upstream device is further configured to send an initialization signaling to the downstream device, where the initialization signaling includes a signaling number and a credit type, and the credit type includes a first type and a second type; the first type of credit card is used for indicating that the message is transmitted, and the second type of credit card is used for indicating a retransmission request.
18. 18. A method of testing, applied to a protocol controller, the protocol controller comprising a stimulus generation module, a transmit path, a stimulus response module, and a receive path, the method comprising: the excitation generation module generates a first test excitation, and transmits the first test excitation to the excitation response module through the transmission path; The excitation response module obtains a first test response based on the first test excitation, and transmits the first test response to the excitation generation module through the receiving channel; The stimulus generation module verifies that the first test response is correct.
19. 19. A computing device, the computing device comprising a protocol controller, the protocol controller comprising a stimulus generation module, a transmit path, a stimulus response module, and a receive path; the excitation generation module is used for generating a first test excitation, and transmitting the first test excitation to the excitation response module through the transmission path; the excitation response module is used for obtaining a first test response based on the first test excitation, and transmitting the first test response to the excitation generation module through the receiving channel; the stimulus generation module is further configured to verify whether the first test response is correct.
20. 20. A chip, characterized in that the chip comprises a protocol controller, wherein the protocol controller comprises an excitation generating module, a transmitting path, an excitation responding module and a receiving path; the excitation generation module is used for generating a first test excitation, and transmitting the first test excitation to the excitation response module through the transmission path; the excitation response module is used for obtaining a first test response based on the first test excitation, and transmitting the first test response to the excitation generation module through the receiving channel; the stimulus generation module is further configured to verify whether the first test response is correct.

Description

Protocol controller, test method, computing device and chip Technical Field The present application relates to the field of chip technologies, and in particular, to a protocol controller, a test method, a computing device, and a chip. Background The CXL (Compute Express Link, computing interconnect express bus) protocol is a new transport protocol that has recently been derived based on the PCIe (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, high speed serial computer expansion bus standard) protocol. The CXL controller is used for managing CXL messages transmitted between devices or between a host and the devices. The related art provides a loopback technique (Loopback) for PCIe controllers that allows PCIe controllers to loop back their issued requests to their own receivers, thus internally testing PCIe controllers without connecting external physical devices. However, the CXL controller is an asymmetric controller, which can only send out requests and receive responses, and cannot receive the requests sent by itself, and directly applying the loop-back technique to test may cause errors. Disclosure of Invention The application provides a protocol controller, a testing method, a computing device and a chip, and the self-testing flow provided by the application can be used for testing a CXL controller, thereby meeting the asymmetric characteristic of the CXL controller. According to one aspect of the present application, there is provided a protocol controller including a stimulus generation module, a transmission path, a stimulus response module, and a reception path; the excitation generation module is used for generating a first test excitation, and transmitting the first test excitation to the excitation response module through the transmission path; the excitation response module is used for obtaining a first test response based on the first test excitation, and transmitting the first test response to the excitation generation module through the receiving channel; the stimulus generation module is further configured to verify whether the first test response is correct. According to an aspect of the present application, there is provided a test method applied to a protocol controller including a stimulus generation module, a transmission path, a stimulus response module, and a reception path, the method comprising: the excitation generation module generates a first test excitation, and transmits the first test excitation to the excitation response module through the transmission path; The excitation response module obtains a first test response based on the first test excitation, and transmits the first test response to the excitation generation module through the receiving channel; The stimulus generation module verifies that the first test response is correct. According to one aspect of the present application, there is provided a computing device comprising a protocol controller, characterized in that the protocol controller comprises a stimulus generation module, a transmit path, a stimulus response module, and a receive path; the excitation generation module is used for generating a first test excitation, and transmitting the first test excitation to the excitation response module through the transmission path; the excitation response module is used for obtaining a first test response based on the first test excitation, and transmitting the first test response to the excitation generation module through the receiving channel; the stimulus generation module is further configured to verify whether the first test response is correct. According to one aspect of the present application, there is provided a chip comprising a protocol controller, characterized in that the protocol controller comprises a stimulus generation module, a transmission path, a stimulus response module and a reception path; the excitation generation module is used for generating a first test excitation, and transmitting the first test excitation to the excitation response module through the transmission path; the excitation response module is used for obtaining a first test response based on the first test excitation, and transmitting the first test response to the excitation generation module through the receiving channel; the stimulus generation module is further configured to verify whether the first test response is correct. According to an aspect of the present application, there is provided a chip comprising the above protocol controller. According to one aspect of the present application, there is provided a computing device comprising the protocol controller described above. The technical scheme provided by the embodiment of the application has the beneficial effects that at least the following are included. In the embodiment of the application, an excitation generating module and an excitation response module are embedded in a protocol controller, so that a self-test flow is realized, namely, a first test excitation gener