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CN-122028308-A - Power supply via design method, device, equipment and storage medium

CN122028308ACN 122028308 ACN122028308 ACN 122028308ACN-122028308-A

Abstract

The application discloses a power supply via hole design method, a device, equipment and a storage medium. The method comprises the steps of dividing a PCB into a plurality of functional areas according to electric functions, distributing a current weight factor, a thermal coupling weight factor and a signal integrity sensitivity weight factor for each functional area, axially dispersing a power via of the PCB into a plurality of micro-element sections which are the same as the number of layers of the PCB, defining a geometric parameter set comprising aperture, side wall copper thickness and anti-bonding pad size for each micro-element section, carrying out iterative optimization on the geometric parameter set of the micro-element sections based on the weight factors of the functional areas to obtain a pareto optimal solution set, selecting a target geometric parameter set from the pareto optimal solution set based on a preset design target of the PCB, and designing the power via of the PCB according to the target geometric parameter set. The application solves the problem of cross-domain failure chain of the traditional constant-diameter power supply via hole design, and has the effect of realizing the system-level collaborative optimization of multiple physical fields and obviously improving the comprehensive performance of the power supply distribution network.

Inventors

  • LIANG JIANGQIANG

Assignees

  • 深圳市晶存科技股份有限公司

Dates

Publication Date
20260512
Application Date
20251231

Claims (10)

  1. 1. A method of power via design, comprising: dividing a PCB to be designed into a plurality of functional areas according to electrical functions, and distributing a current weight factor, a thermal coupling weight factor and a signal integrity sensitivity weight factor to each functional area; axially dispersing the power supply via hole of the PCB into a plurality of micro-element sections with the same layer number as the PCB, and defining a geometric parameter set containing aperture, side wall copper thickness and anti-bonding pad size for each micro-element section; based on the weight factors of the functional areas, performing iterative optimization on the geometric parameter set of the micro-element section to obtain a pareto optimal solution set; And selecting a target geometric parameter set from the pareto optimal solution set based on a preset design target of the PCB, and designing a power supply via hole of the PCB according to the target geometric parameter set.
  2. 2. The power via design method of claim 1, wherein the plurality of functional areas comprises: Chip connection areas partitioned based on interconnect requirements with external chips; A core power supply area divided based on the power distribution network main path requirements; Critical reference land areas partitioned based on high speed signal return path integrity requirements; high-speed signal wiring areas divided based on high-speed signal transmission path requirements.
  3. 3. The method of power via design of claim 1, wherein the step of iteratively optimizing the set of geometric parameters of the micro-segment based on the weight factors of the functional region to obtain a pareto optimal solution set comprises: generating an initial geometric parameter set population according to space filling sampling based on the weight factors of the functional areas within a preset process constraint range, wherein the geometric parameter set population comprises a plurality of geometric parameter set individuals, and each geometric parameter set individual comprises geometric parameter sets of all micro-element sections of a power supply via hole of the PCB; performing physical field simulation of an electromagnetic domain, a circuit domain, a thermal domain and a mechanical domain on each geometrical parameter set to obtain corresponding performance indexes; Calculating the comprehensive adaptability of each geometrical parameter set based on the acquired performance index and a dynamic weight coefficient preset for the performance index; based on the comprehensive fitness of each geometrical parameter set individual, selecting, crossing and mutating the geometrical parameter set population to generate a new generation geometrical parameter set population; Judging whether the geometrical parameter set population of the new generation meets the preset convergence condition, If the preset convergence condition is not met, taking the new generation geometrical parameter set population as the current generation geometrical parameter set population, and returning to the execution step, wherein the physical field simulation of the electromagnetic domain, the circuit domain, the thermal domain and the mechanical domain is executed in parallel for each geometrical parameter set individual to acquire the corresponding performance index; and if the preset convergence condition is met, outputting the non-dominant solution set collected in the iterative optimization process as the pareto optimal solution set.
  4. 4. The power via design method of claim 3, wherein in the step of generating an initial population of geometric parameter sets from space-filling samples based on the weighting factors of the functional regions within a predetermined process constraint, Sampling the aperture and/or the side wall copper thickness of the micro-element section according to the current weight factor and the thermal coupling weight factor of the functional area where the micro-element section is positioned; and sampling the anti-bonding pad size of the micro-segment according to the signal integrity sensitivity factor of the functional area where the micro-segment is positioned.
  5. 5. The power via design method of claim 3, wherein the performance metrics comprise frequency domain impedance, time domain impedance, signal jitter, thermal rise, mechanical stress, and geometric smoothness.
  6. 6. The method of claim 3, wherein in the step of calculating the overall fitness of each individual geometric parameter set based on the obtained performance index and a dynamic weight coefficient preset for the performance index, The initial value of the dynamic weight coefficient is preset according to the preset application scene of the PCB, and in the iterative optimization process, the weight coefficient related to the electrical performance index of the PCB is reduced, and the weight coefficient related to the reliability performance index and the manufacturability performance index of the PCB is increased.
  7. 7. The power via design method of claim 3, wherein the iterative optimization employs a genetic algorithm or a particle swarm optimization algorithm.
  8. 8. A power via design apparatus, comprising: The function dividing module is used for dividing the PCB to be designed into a plurality of functional areas according to the electrical function, and distributing a current weight factor, a thermal coupling weight factor and a signal integrity sensitivity weight factor to each functional area; The parameterized modeling module is used for axially dispersing the power supply via hole of the PCB into a plurality of micro-element sections with the same layer number as the PCB, and defining a geometric parameter set comprising the aperture, the copper thickness of the side wall and the anti-bonding pad size for each micro-element section; the iterative optimization module is used for carrying out iterative optimization on the geometric parameter set of the micro-element section based on the weight factors of the functional area so as to obtain a pareto optimal solution set; And the output module is used for selecting a target geometric parameter set from the pareto optimal solution set based on a preset design target of the PCB, and designing a power supply via hole of the PCB according to the target geometric parameter set.
  9. 9. An electronic device comprising a memory and a processor, wherein: the memory is used for storing a computer program; The processor is configured to read the computer program in the memory and execute the steps of the power via design method according to any one of claims 1 to 7.
  10. 10. A computer-readable storage medium, characterized in that a readable computer program is stored thereon, which program, when being executed by a processor, implements the steps of the power via design method as claimed in any one of claims 1 to 7.

Description

Power supply via design method, device, equipment and storage medium Technical Field The application relates to the technical field of printed circuit board design, in particular to a power supply via hole design method, a device, equipment and a storage medium. Background In the design of high-end electronic systems, power vias are used as key structures for connecting different power layers, and the performance of the power vias directly affects the power integrity, signal integrity and long-term reliability of the whole system. The current electronic equipment is developed towards high frequency, high density and high power, and the design of the traditional power via hole faces serious challenges that under the high frequency application scene, the current is unevenly distributed to cause local hot spot formation, and meanwhile, the electric migration and the thermal mechanical stress concentration are caused to finally form a cross-domain failure chain. Aiming at the problem of power supply via hole design, the prior art adopts a single physical field optimization method, such as a design strategy based on direct current resistance minimization or simply considering high-frequency impedance characteristics. Some improvements have attempted to improve electrical performance by increasing the via size or increasing the number of vias, or to use thermal simulation to guide layout adjustments. However, the prior schemes have obvious defects that a single-field optimization method cannot solve the problem of coupling failure among electric, thermal and mechanical stress, so that reliability and manufacturing feasibility are sacrificed while electric performance is pursued, in a distributed design flow, power integrity and signal integrity designs are mutually fractured, interference of a via structure on an adjacent high-speed signal is difficult to effectively control, a system-level collaborative optimization mechanism is lacking, a global optimal solution cannot be found under the condition that multiple physical fields are mutually restricted, and finally the problem that early failure or performance of a product does not reach standards occurs in practical application. Disclosure of Invention In view of the above, the present application provides a method, apparatus, device and storage medium for designing a power via, so as to solve the above technical problems. In a first aspect, the present application provides a method for designing a power via, including: dividing a PCB to be designed into a plurality of functional areas according to electrical functions, and distributing a current weight factor, a thermal coupling weight factor and a signal integrity sensitivity weight factor to each functional area; axially dispersing the power supply via hole of the PCB into a plurality of micro-element sections with the same layer number as the PCB, and defining a geometric parameter set containing aperture, side wall copper thickness and anti-bonding pad size for each micro-element section; based on the weight factors of the functional areas, performing iterative optimization on the geometric parameter set of the micro-element section to obtain a pareto optimal solution set; And selecting a target geometric parameter set from the pareto optimal solution set based on a preset design target of the PCB, and designing a power supply via hole of the PCB according to the target geometric parameter set. In some embodiments, the plurality of functional areas includes: Chip connection areas partitioned based on interconnect requirements with external chips; A core power supply area divided based on the power distribution network main path requirements; Critical reference land areas partitioned based on high speed signal return path integrity requirements; high-speed signal wiring areas divided based on high-speed signal transmission path requirements. In some embodiments, the step of iteratively optimizing the geometric parameter set of the micro-segment based on the weight factor of the functional region to obtain the pareto optimal solution set includes: generating an initial geometric parameter set population according to space filling sampling based on the weight factors of the functional areas within a preset process constraint range, wherein the geometric parameter set population comprises a plurality of geometric parameter set individuals, and each geometric parameter set individual comprises geometric parameter sets of all micro-element sections of a power supply via hole of the PCB; performing physical field simulation of an electromagnetic domain, a circuit domain, a thermal domain and a mechanical domain on each geometrical parameter set to obtain corresponding performance indexes; Calculating the comprehensive adaptability of each geometrical parameter set based on the acquired performance index and a dynamic weight coefficient preset for the performance index; based on the comprehensive fitness of each ge