CN-122028407-A - Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

A semiconductor device includes at least one memory cell including a first transistor and a second transistor stacked vertically, the first transistor and the second transistor being vertical channel transistors, a first semiconductor layer of the first transistor including an annular first sidewall of an opening extending in a direction perpendicular to a substrate, a first gate electrode including an annular second sidewall of the opening extending in the direction perpendicular to the substrate, the first sidewall surrounding the second sidewall, and a second semiconductor layer of the second transistor including an annular third sidewall of the opening extending in the direction perpendicular to the substrate. According to the scheme provided by the embodiment of the disclosure, the memory cell comprises two vertically-stacked vertical channel transistors, so that the area of the memory cell can be reduced, and high-density integration is realized.

Inventors

• DONG BOWEN
• DAI JIN
• Lv Haochang
• LI GENGFEI
• WANG GUILEI

Assignees

• 北京超弦存储器研究院

Dates

Publication Date

20260512

Application Date

20241105

Claims (16)

1. 1. The semiconductor device is characterized by comprising at least one storage unit, wherein the storage unit comprises a first transistor and a second transistor which are stacked on a substrate along the direction perpendicular to the substrate, the second transistor is arranged on one side of the first transistor, which is away from the substrate, the first transistor comprises a first gate electrode, a first electrode, a second electrode and a first semiconductor layer, the first semiconductor layer is respectively connected with the first electrode and the second electrode, the second electrode is arranged on one side of the first electrode, which is away from the substrate, the second transistor comprises a third electrode and a second semiconductor layer, the second semiconductor layer is respectively connected with the third electrode and the first gate electrode, and the third electrode is arranged on one side of the first gate electrode, which is away from the substrate; The first semiconductor layer comprises a first side wall extending along the direction perpendicular to the substrate, and the cross section of the first side wall parallel to the substrate is of an open annular structure; The first gate electrode comprises a second side wall extending along the direction perpendicular to the substrate, the section of the second side wall parallel to the substrate is of an open annular structure, and the first side wall surrounds the second side wall; The second semiconductor layer comprises a third side wall extending along the direction perpendicular to the substrate, and the cross section of the third side wall parallel to the substrate is of an open annular structure.
2. 2. The semiconductor device according to claim 1, wherein the first semiconductor layer further includes a first bottom wall which is connected to the first side wall and closes the first side wall toward a substrate side and parallel to the substrate; The first gate electrode further comprises second bottom walls which are distributed on one side of the first bottom walls, which is away from the substrate, and are parallel to the substrate, wherein the second bottom walls are connected with the second side walls and close one side of the second side walls, which is towards the substrate.
3. 3. The semiconductor device according to claim 2, wherein the second semiconductor layer further includes a third bottom wall connected to the third side wall and closing a side of the third side wall facing the substrate and parallel to the substrate, and wherein the first gate electrode is connected to the third bottom wall facing the substrate.
4. 4. The semiconductor device according to claim 3, wherein the memory cell further comprises a first gate insulating layer provided between the first semiconductor layer and the first gate electrode, a second bottom wall wrapping the first gate electrode toward a substrate side and an outer side wall of the second side wall, and an outer side wall wrapping a third side wall of the second semiconductor layer.
5. 5. The semiconductor device according to claim 4, wherein the first gate insulating layer includes a first horizontal portion distributed on a side of the first bottom wall facing away from the substrate, a first vertical portion distributed on an inner side wall of the first side wall, a second horizontal portion distributed on a side of the first side wall facing away from the substrate, and a second vertical portion extending from the second horizontal portion in a direction perpendicular to the substrate, which are sequentially connected, and an orthographic projection of the second vertical portion on the substrate falls within an orthographic projection of the first side wall on the substrate.
6. 6. The semiconductor device of claim 4, wherein the second sidewall includes a first sub-sidewall surrounded by the first sidewall and a second sub-sidewall extending from the first sub-sidewall toward a side facing away from the substrate and not surrounded by the first sidewall; The memory cell further includes a control electrode disposed on a side of the first gate insulating layer facing away from the first gate electrode, the control electrode surrounding an outer sidewall of the second sub-sidewall.
7. 7. The semiconductor device according to claim 6, wherein the second transistor further includes a second gate electrode provided on a side of the first gate insulating layer facing away from the second semiconductor layer, the second gate electrode surrounding an outer sidewall of the third sidewall of the second semiconductor layer.
8. 8. The semiconductor device according to claim 7, wherein the second electrode surrounds an outer sidewall of the first semiconductor layer.
9. 9. The semiconductor device of claim 3, wherein the first electrode extends in a first direction parallel to the substrate and is connected to a side of the first bottom wall facing the substrate, and wherein the third electrode extends in the first direction and is connected to a side of the third sidewall facing away from the substrate.
10. 10. The semiconductor device according to claim 4, wherein an orthographic projection of the first gate electrode, the first gate insulating layer, and the second semiconductor layer on the substrate is located within an orthographic projection of the first semiconductor layer on the substrate.
11. 11. The semiconductor device according to claim 7 or 8, wherein the semiconductor device comprises at least one layer of memory cell array, each layer of the memory cell array comprises a plurality of memory cells distributed along a first direction parallel to a substrate and a second direction parallel to the substrate, the first electrodes of the first transistors of the same row distributed along the first direction are connected to form a first bit line of an integrated structure, the third electrodes of the second transistors of the same row are connected to form a second bit line of an integrated structure, the control electrodes of the memory cells of the same column distributed along the second direction are connected to form a first word line of an integrated structure, the second gate electrodes of the second transistors of the same column are connected to form a second word line of an integrated structure, the second electrodes of the first transistors of the same column are connected to form a reference signal line of an integrated structure, and the first direction and the second direction cross.
12. 12. The semiconductor device according to claim 11, wherein the first semiconductor layer, the first gate insulating layer, the first gate electrode, and the second semiconductor layer of two memory cells adjacent in the first direction are disposed in the same hole, and openings of two open ring structures formed by the two first semiconductor layers of two memory cells are disposed opposite to each other in the first direction, and openings of two open ring structures formed by the two second semiconductor layers of two memory cells are disposed opposite to each other in the first direction.
13. 13. A method of manufacturing a semiconductor device, comprising: forming a first electrode on a substrate; Forming a second electrode of a first transistor, a first semiconductor layer connected with the second electrode and a first gate electrode on one side of the first electrode, which is far away from the substrate, wherein the first semiconductor layer comprises a first side wall extending along the direction vertical to the substrate, and the cross section of the first side wall parallel to the substrate is of an open annular structure; forming a second semiconductor layer on one side of the first gate electrode, which is far away from the substrate, wherein the second semiconductor layer comprises a third side wall extending along the direction vertical to the substrate, and the section of the third side wall, which is parallel to the substrate, is of an open annular structure; And forming a third electrode connected with the second semiconductor layer on one side of the second semiconductor layer away from the substrate.
14. 14. The method for manufacturing a semiconductor device according to claim 13, wherein the forming a first electrode over the substrate comprises: Forming a plurality of first bit lines on the substrate, wherein the first bit lines extend along a first direction parallel to the substrate and are distributed at intervals along a second direction parallel to the substrate, and the first bit lines comprise a plurality of first electrodes, and the first direction and the second direction are intersected; the forming of the second electrode of the first transistor, the first semiconductor layer connected with the second electrode and the first gate electrode on the side of the first electrode facing away from the substrate, and the forming of the second semiconductor layer on the side of the first gate electrode facing away from the substrate includes: Forming a stacked structure on one side of the first bit line, which is far away from the substrate, wherein the stacked structure comprises a first conductive layer, and the orthographic projection of the first conductive layer on the substrate overlaps with orthographic projections of a plurality of first bit lines on the substrate; forming a plurality of first holes penetrating through the stacked structure along a direction perpendicular to a substrate and distributed at intervals along the first direction, wherein the bottom wall of each first hole exposes one first bit line, the orthographic projection of the first hole on the substrate is positioned in the orthographic projection of the first conductive layer on the substrate, and the side wall of the first hole exposes the first conductive layer; Forming a first semiconductor structure layer covering a region, which is smaller than or equal to a first preset height, on the bottom wall of the first hole and the side wall of the first hole, wherein the distance between the first semiconductor structure layer and the substrate is smaller than or equal to a first preset height, and the first preset height is larger than the distance between the surface, away from the substrate, of the first conductive layer and the substrate; Forming a first grid electrode insulating structure layer and a first grid electrode structure layer which sequentially cover the bottom wall and the side wall of the first hole formed with the first semiconductor structure layer, and a first isolation layer filling the first hole, and back-etching the first grid electrode structure layer and the first isolation layer to a position with a second preset height from the substrate to form a first sub-hole, wherein the second preset height is larger than the first preset height; forming a second semiconductor structure layer covering the bottom wall and the side wall of the first sub-hole; Forming a second isolation groove extending along a second direction and penetrating through the stacked structure along a direction perpendicular to the substrate, wherein the second isolation groove divides the first semiconductor structure layer, the first gate insulation structure layer, the first gate electrode structure layer and the second semiconductor structure layer into two independent parts which are distributed at intervals along the first direction, the first conductive layer is divided into two reference signal lines extending along the second direction and distributed at intervals along the first direction, and the reference signal lines comprise a plurality of second electrodes.
15. 15. The method for manufacturing a semiconductor device according to claim 14, wherein, The stacked structure further comprises a second conductive layer and a third conductive layer which are sequentially arranged on one side, away from the substrate, of the first conductive layer, the second conductive layer and the third conductive layer are distributed at intervals along the direction perpendicular to the substrate, and the second conductive layer and the third conductive layer extend along the second direction parallel to the substrate; The front projection of the first hole on the substrate is positioned in the front projection of the second conductive layer on the substrate, and the side wall of the first hole is positioned in the front projection of the third conductive layer on the substrate, the second conductive layer and the third conductive layer are also exposed out of the side wall of the first hole, the first preset height is smaller than the distance between the surface of the second conductive layer facing the substrate and the substrate, the second preset height is larger than the distance between the surface of the second conductive layer facing away from the substrate and the substrate, and is smaller than the distance between the surface of the third conductive layer facing the substrate and the substrate; The second isolation groove also divides the second conductive layer into two first word lines which extend along the second direction and are distributed at intervals along the first direction, and the third conductive layer is divided into two second word lines which extend along the second direction and are distributed at intervals along the first direction.
16. 16. An electronic apparatus comprising the semiconductor device according to any one of claims 1 to 12, or a semiconductor device formed according to the method for manufacturing a semiconductor device according to any one of claims 13 to 15.

Description

Semiconductor device, manufacturing method thereof and electronic equipment Technical Field Embodiments of the present disclosure relate to device design and fabrication thereof, and more particularly to a semiconductor device, a fabrication method thereof, and an electronic device. Background With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing, so that any minor differences in process production may affect the performance of the devices. In order to reduce the cost of the product as much as possible, it is desirable to make as many device cells as possible on a limited substrate. Since moore's law emerged, various semiconductor structural designs and process optimizations have been proposed in the industry to meet the needs of people for current products. Disclosure of Invention The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims. The application provides a semiconductor device, a manufacturing method thereof and electronic equipment, which reduce the area of a memory cell and improve the memory density. The embodiment of the application provides a semiconductor device, which comprises at least one memory cell, wherein the memory cell comprises a first transistor and a second transistor which are stacked on a substrate along the direction vertical to the substrate, the second transistor is arranged on one side of the first transistor, which is away from the substrate, the first transistor comprises a first gate electrode, a first electrode, a second electrode and a first semiconductor layer, the first semiconductor layer is respectively connected with the first electrode and the second electrode, the second electrode is arranged on one side of the first electrode, which is away from the substrate, the second transistor comprises a third electrode and a second semiconductor layer, the second semiconductor layer is respectively connected with the third electrode and the first gate electrode, and the third electrode is arranged on one side of the first gate electrode, which is away from the substrate; The first semiconductor layer comprises a first side wall extending along the direction perpendicular to the substrate, and the cross section of the first side wall parallel to the substrate is of an open annular structure; The first gate electrode comprises a second side wall extending along the direction perpendicular to the substrate, the section of the second side wall parallel to the substrate is of an open annular structure, and the first side wall surrounds the second side wall; The second semiconductor layer comprises a third side wall extending along the direction perpendicular to the substrate, and the cross section of the third side wall parallel to the substrate is of an open annular structure. In some embodiments, the first semiconductor layer further comprises a first bottom wall connected to and closing a side of the first sidewall facing a substrate and parallel to the substrate; The first gate electrode further comprises second bottom walls which are distributed on one side of the first bottom walls, which is away from the substrate, and are parallel to the substrate, wherein the second bottom walls are connected with the second side walls and close one side of the second side walls, which is towards the substrate. In some embodiments, the second semiconductor layer further includes a third bottom wall connected to and closing a side of the third sidewall facing the substrate and parallel to the substrate, the first gate electrode being connected to the side of the third bottom wall facing the substrate. In some embodiments, the memory cell further includes a first gate insulating layer disposed between the first semiconductor layer and the first gate electrode, wrapping a second bottom wall of the first gate electrode toward a side of the substrate and an outer sidewall of the second sidewall, and wrapping an outer sidewall of a third sidewall of the second semiconductor layer. In some embodiments, the first gate insulating layer includes a first horizontal portion distributed on a side of the first bottom wall facing away from the substrate, a first vertical portion distributed on an inner sidewall of the first sidewall, a second horizontal portion distributed on a side of the first sidewall facing away from the substrate, and a second vertical portion extending from the second horizontal portion along a direction perpendicular to the substrate, wherein an orthographic projection of the second vertical portion on the substrate falls into an orthographic projection of the first sidewall on the substrate. In some embodiments, the second sidewall includes a first sub-sidewall surrounded by the first sidewall and a second sub-sidewall extending from the first sub-sidewall toward a s