CN-122028408-A - Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

A semiconductor device comprises at least one memory cell, wherein the memory cell comprises a first transistor and a second transistor which are vertically stacked, the first transistor and the second transistor are vertical channel transistors, a second semiconductor layer of the second transistor is connected with a first gate electrode of the first transistor, the first semiconductor layer of the first transistor comprises a first vertical part which vertically extends, the second semiconductor layer of the second transistor comprises a second vertical part which vertically extends, the first gate electrode is distributed on the side wall of the first vertical part, the first electrode and the third electrode extend along a first direction which is parallel to a substrate, the second gate electrode and the third gate electrode extend along a second direction which is parallel to the substrate, and the first direction and the second direction are intersected. According to the scheme provided by the embodiment of the disclosure, the memory cell comprises two vertically-stacked vertical channel transistors, so that the area of the memory cell can be reduced, and high-density integration is realized.

Inventors

• DONG BOWEN
• YANG FUWANG
• Lv Haochang
• LI GENGFEI
• WANG GUILEI

Assignees

• 北京超弦存储器研究院

Dates

Publication Date

20260512

Application Date

20241105

Claims (16)

1. 1. The semiconductor device is characterized by comprising at least one storage unit, wherein the storage unit comprises a first transistor and a second transistor which are stacked on a substrate along the direction perpendicular to the substrate, the second transistor is arranged on one side, away from the substrate, of the first transistor, the first transistor comprises a first gate electrode, a second gate electrode, a first electrode, a second electrode and a first semiconductor layer, the first semiconductor layer is respectively connected with the first electrode and the second electrode, the second electrode is arranged on one side, away from the substrate, of the first electrode, the second transistor comprises a third gate electrode, a third electrode and a second semiconductor layer, the second semiconductor layer is respectively connected with the third electrode and the first gate electrode, the third electrode is arranged on one side, away from the substrate, of the first gate electrode, and the second semiconductor layer comprises metal oxide; The first semiconductor layer comprises a first vertical part extending along the direction vertical to the substrate, the second semiconductor layer comprises a second vertical part extending along the direction vertical to the substrate, and the first gate electrode is distributed on the side wall of the first vertical part; The second gate electrode is distributed on the side wall of the first vertical part, and the third gate electrode is distributed on the side wall of the second vertical part; the first electrode and the third electrode extend in a first direction parallel to a substrate, and the second gate electrode and the third gate electrode extend in a second direction parallel to the substrate, the first direction and the second direction intersecting.
2. 2. The semiconductor device according to claim 1, wherein the first semiconductor layer further includes a first horizontal portion extending in a direction parallel to the substrate, the first horizontal portion being connected to an end of the first vertical portion toward the substrate side, the second semiconductor layer further includes a second horizontal portion extending in a direction parallel to the substrate, the second horizontal portion being connected to an end of the second vertical portion toward the substrate side, and the first gate electrode is further distributed on a side of the first horizontal portion facing away from the substrate.
3. 3. The semiconductor device according to claim 2, wherein the first horizontal portion and the first vertical portion are distributed along the first direction, the second horizontal portion and the second vertical portion are distributed along the first direction, an orthographic projection of the first horizontal portion on the substrate overlaps an orthographic projection of the second horizontal portion on the substrate, and the first vertical portion and the second vertical portion are disposed on the same side of the second horizontal portion.
4. 4. The semiconductor device of claim 1, wherein the second electrode is disposed on the first vertical sidewall on a side of the second gate electrode facing away from the substrate, the second electrode extending in the second direction.
5. 5. The semiconductor device of claim 4, wherein an orthographic projection of the second electrode at the substrate overlaps with an orthographic projection of the third gate electrode at the substrate.
6. 6. The semiconductor device according to claim 2, wherein the first electrode is connected to a side of the first horizontal portion facing the substrate, and the third electrode is connected to a side of the second vertical portion facing away from the substrate.
7. 7. A semiconductor device according to claim 2 or 3, wherein the memory cell further comprises a first gate insulating layer arranged between the first semiconductor layer and the first gate electrode, extending continuously on the side of the first horizontal portion facing away from the substrate, the side wall of the first vertical portion facing towards the first horizontal portion and the side of the first vertical portion facing away from the substrate, and extending to cover the side wall of the second vertical portion facing away from the second horizontal portion.
8. 8. The semiconductor device of claim 7, wherein an orthographic projection of the first gate electrode, the first gate insulating layer, the second semiconductor layer on a substrate is located within the orthographic projection of the first semiconductor layer on the substrate.
9. 9. The semiconductor device according to any one of claims 1 to 6, wherein the memory cell further includes a second gate insulating layer provided on a side wall of the first vertical portion, the second gate insulating layer forming a trench having an opening direction parallel to the substrate and facing away from the first semiconductor layer, the second gate electrode filling the trench.
10. 10. The semiconductor device of claim 9, wherein the semiconductor device comprises at least one layer of memory cell array, each layer of the memory cell array comprises a plurality of memory cells distributed along the first direction and the second direction, the first electrodes of the first transistors of the memory cells of the same row distributed along the first direction are connected to form a first bit line of an integral structure, the third electrodes of the second transistors of the memory cells of the same row are connected to form a second bit line of an integral structure, the second gate electrodes of the first transistors of the memory cells of the same column distributed along the second direction are connected to form a first word line of an integral structure, the third gate electrodes of the second transistors of the memory cells of the same column are connected to form a second word line of an integral structure, and the second electrodes of the first transistors of the same column are connected to form a reference signal line of an integral structure.
11. 11. The semiconductor device of claim 10, wherein the second gate insulating layers of the first transistors of the memory cells in a same column are connected to form a unitary structure.
12. 12. The semiconductor device of claim 10, wherein memory cells of each adjacent two columns are mirror symmetrically distributed along the first direction.
13. 13. A method of manufacturing a semiconductor device, comprising: Forming a first electrode on a substrate extending in a first direction parallel to the substrate; Forming a first semiconductor layer connected with the first electrode on one side of the first electrode away from the substrate, wherein the first semiconductor layer comprises a first vertical part extending along a direction perpendicular to the substrate; Forming a first gate electrode spaced apart from the first semiconductor layer and distributed on a sidewall of the first vertical portion; forming a second semiconductor layer connected with the first gate electrode on one side of the first gate electrode away from the substrate, wherein the second semiconductor layer comprises a second vertical part extending along the direction perpendicular to the substrate; Forming a third electrode which is connected with the second semiconductor layer and extends along the first direction on one side of the second semiconductor layer away from the substrate; And forming a second electrode connected with the first semiconductor layer on one side of the first electrode, which is away from the substrate, forming a second gate electrode extending along a second direction parallel to the substrate on the side wall of the first vertical part, and forming a third gate electrode extending along the second direction on the side wall of the second vertical part, wherein the first direction and the second direction are intersected.
14. 14. The method for manufacturing a semiconductor device according to claim 13, wherein the forming a first electrode extending in a first direction parallel to the substrate over the substrate comprises: forming a plurality of first bit lines extending along the first direction and spaced apart along the second direction on the substrate, the first bit lines including a plurality of first electrodes; the forming a first semiconductor layer connected with the first electrode on one side of the first electrode away from the substrate, forming a first gate electrode which is spaced from the first semiconductor layer and is distributed on the side wall of the first vertical part, and forming a second semiconductor layer connected with the first gate electrode on one side of the first gate electrode away from the substrate comprises the following steps: Forming a first dummy layer, a second dummy layer and a third dummy layer which are stacked in sequence and distributed at intervals along the direction perpendicular to the substrate on one side of the first bit line, which is away from the substrate, wherein the first dummy layer, the second dummy layer and the third dummy layer extend along the second direction, and the orthographic projection of the first dummy layer on the substrate, the orthographic projection of the second dummy layer on the substrate and the orthographic projection of the third dummy layer on the substrate overlap with the orthographic projections of a plurality of first bit lines on the substrate; Forming a first isolation groove penetrating through the first dummy layer, the second dummy layer and the third dummy layer along the direction perpendicular to the substrate and extending along the second direction, wherein the bottom wall of the first isolation groove exposes a plurality of first bit lines, and two side walls of the first isolation groove, which are oppositely arranged, expose the first dummy layer, the second dummy layer and the third dummy layer; Forming a first semiconductor structure layer covering the bottom wall and part of the side wall of the first isolation groove, wherein the first semiconductor structure layer covers a region, on the side wall of the first isolation groove, of which the distance from the substrate is smaller than or equal to a first preset height, and the first preset height is larger than the distance from the surface of the second dummy layer, which is away from the substrate, to the substrate and smaller than the distance from the surface of the third dummy layer, which is towards the substrate, to the substrate; forming a first grid insulation structure layer and a first grid electrode structure layer which sequentially cover the bottom wall and the side wall of the first isolation groove formed with the first semiconductor structure layer, and filling the first isolation layer of the first isolation groove, and back-etching the first grid electrode structure layer and the first isolation layer to a position with a second preset height from the substrate, wherein the second preset height is larger than the first preset height and smaller than the distance between the surface of the third dummy layer facing the substrate and the substrate; forming a second semiconductor structure layer covering the bottom wall and the side wall of the first sub-trench; And forming a second isolation groove, wherein the second isolation groove comprises a second sub-groove extending along the second direction and a plurality of third sub-grooves extending along the first direction and distributed at intervals along the second direction, the second sub-groove divides the first semiconductor structure layer, the first gate insulation structure layer, the first gate electrode structure layer and the second semiconductor structure layer into two independent parts along the second direction, and the third sub-groove divides each part into a plurality of sections distributed at intervals along the second direction, and each section comprises a first semiconductor layer, a first gate insulation layer, a first gate electrode and a second semiconductor layer of one memory cell.
15. 15. The method for manufacturing a semiconductor device according to claim 14, wherein the forming a second electrode connected to the first semiconductor layer on a side of the first electrode facing away from the substrate comprises: Removing the second dummy layer to form a second lateral groove, and forming a reference signal line which is arranged in the second lateral groove and connected with the plurality of first semiconductor layers, wherein the reference signal line comprises a plurality of second electrodes; Forming a second gate electrode extending in a second direction parallel to a substrate on a side wall of the first vertical portion, forming a third gate electrode extending in the second direction on a side wall of the second vertical portion includes removing the third dummy layer, forming a first lateral trench, forming a second word line disposed in the first lateral trench, the second word line including a plurality of the third gate electrodes; And removing the first dummy layer, forming a third transverse groove, forming a second gate insulating layer covering the inner wall of the third transverse groove and a first word line filling the third transverse groove, wherein the first word line comprises a plurality of second gate electrodes.
16. 16. An electronic apparatus comprising the semiconductor device according to any one of claims 1 to 12, or a semiconductor device formed according to the method for manufacturing a semiconductor device according to any one of claims 13 to 15.

Description

Semiconductor device, manufacturing method thereof and electronic equipment Technical Field Embodiments of the present disclosure relate to device design and fabrication thereof, and more particularly to a semiconductor device, a fabrication method thereof, and an electronic device. Background With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing, so that any minor differences in process production may affect the performance of the devices. In order to reduce the cost of the product as much as possible, it is desirable to make as many device cells as possible on a limited substrate. Since moore's law emerged, various semiconductor structural designs and process optimizations have been proposed in the industry to meet the needs of people for current products. Disclosure of Invention The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims. The application provides a semiconductor device, a manufacturing method thereof and electronic equipment, which reduce the area of a memory cell and improve the memory density. The embodiment of the disclosure provides a semiconductor device, which comprises at least one memory cell, wherein the memory cell comprises a first transistor and a second transistor which are stacked on a substrate along the direction perpendicular to the substrate, the second transistor is arranged on one side, away from the substrate, of the first transistor, the first transistor comprises a first gate electrode, a second gate electrode, a first electrode, a second electrode and a first semiconductor layer, the first semiconductor layer is respectively connected with the first electrode and the second electrode, the second electrode is arranged on one side, away from the substrate, of the first electrode, the second transistor comprises a third gate electrode, a third electrode and a second semiconductor layer, the second semiconductor layer is respectively connected with the third electrode and the first gate electrode, the third electrode is arranged on one side, away from the substrate, of the first gate electrode, and the second semiconductor layer comprises metal oxide; The first semiconductor layer comprises a first vertical part extending along the direction vertical to the substrate, the second semiconductor layer comprises a second vertical part extending along the direction vertical to the substrate, and the first gate electrode is distributed on the side wall of the first vertical part; The second gate electrode is distributed on the side wall of the first vertical part, and the third gate electrode is distributed on the side wall of the second vertical part; The first electrode and the third electrode extend in a first direction parallel to a substrate, and the second gate electrode and the third gate electrode extend in a second direction parallel to the substrate, the first direction and the second direction intersecting. In some embodiments, the first semiconductor layer further includes a first horizontal portion extending in a direction parallel to the substrate, the first horizontal portion being connected to an end of the first vertical portion facing the substrate side, the second semiconductor layer further includes a second horizontal portion extending in a direction parallel to the substrate, the second horizontal portion being connected to an end of the second vertical portion facing the substrate side, and the first gate electrode is further distributed on a side of the first horizontal portion facing away from the substrate. In some embodiments, the first horizontal portion and the first vertical portion are distributed along the first direction, the second horizontal portion and the second vertical portion are distributed along the first direction, the orthographic projection of the first horizontal portion on the substrate overlaps with the orthographic projection of the second horizontal portion on the substrate, and the first vertical portion and the second vertical portion are disposed on the same side of the second horizontal portion. In some embodiments, the second electrode is disposed on the first vertical sidewall on a side of the second gate electrode facing away from the substrate, the second electrode extending in the second direction. In some embodiments, there is overlap between the orthographic projection of the second electrode on the substrate and the orthographic projection of the third gate electrode on the substrate. In some embodiments, the first electrode is connected to a side of the first horizontal portion facing the substrate, and the third electrode is connected to a side of the second vertical portion facing away from the substrate. In some embodiments, the memory cell further includes a first gate insulating layer disposed between