CN-122028409-A - Memory array, preparation method thereof, memory and electronic equipment

CN122028409ACN 122028409 ACN122028409 ACN 122028409ACN-122028409-A

Abstract

The application provides a memory array, a preparation method thereof, a memory and electronic equipment, and relates to the technical field of data storage. The memory array includes a substrate and a plurality of memory cells, each memory cell in turn including a transistor, which in turn includes a source, a drain, a gate, and a channel. The source electrode comprises a source electrode doped region formed in the substrate, the drain electrode comprises a metal silicide layer, the channel is positioned in the substrate, one side of the channel is in contact with the metal silicide layer, and the other side of the channel is in contact with the source electrode doped region. The grid electrode is arranged on the channel. According to the application, one side of the metal silicide layer of the drain electrode is contacted with the channel, so that a Schottky junction can be formed between the metal silicide layer and the channel, thereby increasing the electric field strength of the drain electrode region, reducing the voltage required by collision ionization and further reducing the starting voltage and the driving energy consumption of the device.

Inventors

WANG FANGWEI
HOU CHAOZHAO
Nie Xiaoang
HE ZIFANG
DONG YAOQI
XU JUNHAO

Assignees

华为技术有限公司

Dates

Publication Date: 20260512
Application Date: 20241111

Claims (14)

1. A memory array comprises a substrate and a plurality of memory cells, wherein each memory cell comprises a transistor, and the transistor comprises a source electrode, a drain electrode, a grid electrode and a channel; The source electrode comprises a source doped region formed in the substrate; The drain electrode comprises a metal silicide layer, and a region of the substrate between the source doped region and the metal silicide layer forms the channel; And the grid electrode is arranged on the channel.
2. The memory array of claim 1, wherein the metal silicide layer comprises a first portion; The first portion is located on a side of the channel facing away from the source doped region.
3. The memory array of claim 2, wherein the metal silicide layer further comprises a second portion; The second portion is located on a side of the channel facing away from the substrate, and the second portion is connected with the first portion.
4. A memory array according to claim 3, wherein the second portion is spaced apart from the gate electrode in a direction parallel to the surface of the substrate.
5. The memory array of claim 3 or 4, wherein the transistor further comprises a gate insulating layer; The gate insulating layer is provided between the gate and the channel.
6. The memory array of any one of claims 2-5, A dielectric layer is arranged on one side of the first part, which is away from the channel; The metal silicide layer further includes a third portion stacked between the dielectric layer and the substrate, the third portion being connected to the first portion.
7. The memory array of any one of claims 1-6, wherein, The source doped region is a P-type doped region, and the metal silicide layer comprises a first metal material, and the work function of the first metal material is greater than or equal to 4.5eV; Or the source doped region is an N-type doped region, and the metal silicide layer comprises a second metal material, and the work function of the second metal material is smaller than or equal to 4.5eV.
8. The memory array of claim 7, wherein the memory array is configured to store, The source electrode doping region is a P-type doping region, and the first metal material comprises at least one of titanium nitride, gold, ruthenium, nickel, platinum, cobalt or tungsten; the source doped region is an N-type doped region, and the second metal material comprises at least one of silver, scandium, titanium, aluminum or erbium.
9. The memory array of any one of claims 1-8, wherein, The memory cells include 1T0C memory cells.
10. A memory, comprising: A controller, and The memory array of any one of claims 1-9, the controller being electrically connected to the memory array, the controller being configured to control reading from and writing to the memory array.
11. An electronic device, comprising: Processor, and The memory of claim 10, the processor being electrically connected to the memory, the memory for storing data generated by the processor.
12. A method of manufacturing a memory array, the method comprising: Forming a plurality of memory cells on a substrate, each memory cell including a transistor; The transistor is manufactured by the following steps: preparing a source electrode, wherein the source electrode comprises a source doped region formed in the substrate; Preparing a drain electrode, wherein the drain electrode comprises a metal silicide layer, and a region of the substrate between the source doped region and the metal silicide layer forms a channel of the transistor; a gate is made, the gate being disposed over the channel.
13. The method of claim 12, wherein the memory array is fabricated by, Before the transistor is manufactured, the manufacturing method further comprises the following steps: Dividing a plurality of storage areas which are isolated from each other on the substrate, wherein grooves are formed between two adjacent storage areas; The transistor is manufactured and comprises: preparing the source electrode and the drain electrode in the storage area; Preparing the metal silicide layer, comprising: And preparing a first part on the wall surface of the groove, which is close to the channel, preparing a third part on the wall surface of the groove, which is close to the substrate, and preparing a second part on the side, which is away from the substrate, of the channel, wherein the first part is connected between the second part and the third part.
14. The method of claim 13, wherein the memory array is fabricated by a method comprising, Producing the second portion, comprising: A gap is provided between the second portion and the gate to separate the second portion from the gate.

Description

Memory array, preparation method thereof, memory and electronic equipment Technical Field The present application relates to the field of data storage technologies, and in particular, to a storage array, a preparation method thereof, a memory, and an electronic device. Background In a conventional memory represented by a dynamic random access memory (Dynamic Random Access Memory, DRAM), a memory cell is generally in a single transistor non-capacitance (One transistor capacitor-less,1T 1C) structure, that is, includes a transistor and a capacitor. However, with the increase in integration density of semiconductor memory devices, such memory cells that store charge using capacitors have become an obstacle to reducing the layout of semiconductor memories. In order to achieve higher packing density and integration, memories have been disclosed that use transistors rather than capacitors to store data (i.e., capacitor-less memories). Fig. 1 is a schematic diagram showing a cross-sectional view of a conventional capacitor-less memory, in which a PNP or NPN Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) structure is fabricated on a silicon (Silicon On Insulator, SOI) substrate on an insulating layer, and charges can be stored and read by a floating body effect. In such conventional capacitor-less memories, highly doped regions are typically used in the source and drain regions, respectively, to form ohmic contacts in order to reduce contact resistance. While this design helps to reduce the loss of current through the contact area, it also results in a larger turn-on voltage required to cause impact ionization, and thus greater drive power consumption. Disclosure of Invention The application provides a memory array, a preparation method thereof, a memory and electronic equipment. The purpose is to reduce the turn-on voltage and drive power consumption of the device by increasing the electric field strength of the drain region to reduce the voltage required for impact ionization. In order to achieve the above purpose, the embodiment of the present application adopts the following technical scheme: in one aspect, the present application provides a memory array, such as a dynamic memory array or a static memory array. The memory array comprises a substrate and a plurality of memory cells, wherein each memory cell comprises a transistor, the transistor comprises a source electrode, a drain electrode, a grid electrode and a channel, the source electrode comprises a source doped region formed in the substrate, the drain electrode comprises a metal silicide layer, a region, located between the source doped region and the metal silicide layer, of the substrate forms the channel, and the grid electrode is arranged on the channel. In the memory array of the present application, the drain of the transistor of the memory cell includes a metal silicide layer. That is, the transistor of the present application does not use a doped region to form a drain, but uses a drain including a metal silicide layer. Meanwhile, the application also enables the region of the substrate between the source doped region and the metal silicide layer to form a channel. That is, one side of the channel is in contact with the source doped region and the other side is in contact with the metal silicide layer, and a schottky junction may be formed between the metal silicide layer and the channel. The schottky contact has a lower barrier height and a higher electric field strength, so that the electric field distribution of the drain region is more concentrated under the same voltage, and the concentrated electric field distribution is helpful to enhance the impact ionization effect (i.e. carriers are more likely to collide with lattice atoms when moving in a channel, thereby generating new electron-hole pairs), so that the application can induce more remarkable impact ionization effect by adopting a lower voltage, and further reduce the starting voltage required for causing impact ionization. Because the Schottky contact reduces the starting voltage required by collision ionization, the memory array can work normally under lower voltage, and the driving energy consumption of the device is reduced. In one implementation, the metal silicide layer includes a first portion that is located on a side of the channel facing away from the source doped region. That is, the metal silicide layer may include a first portion on a side of the channel facing away from the source doped region. In this way, the first portion may be in contact with a side of the channel facing away from the source doped region. According to the application, the first part is contacted with the channel, so that the Schottky contact can be formed at the contact interface of the first part and the channel, the electric field intensity of the transistor in the drain region is improved, the impact ionization effect is enhanced, and the starting voltage required by impact ionizatio