CN-122028410-A - Semiconductor device and method for manufacturing the same

Abstract

The embodiment of the disclosure provides a semiconductor device and a manufacturing method thereof, wherein the semiconductor device comprises a plurality of active areas arranged in a first area, each active area comprises a first connecting end and a second connecting end, a plurality of first capacitors arranged in the first area, each first capacitor comprises a first upper electrode and a first lower electrode, the first lower electrode of each first capacitor is connected with each first connecting end, a plurality of second capacitors arranged in a second area, each second capacitor comprises a second upper electrode and a second lower electrode, a plurality of first bonding pads are arranged in the first area, at least one first bonding pad is connected with the second connecting end of at least one active area, and a plurality of second bonding pads are arranged in the second area, and at least one second bonding pad is connected with the second lower electrode of at least one second capacitor. The semiconductor device provided by the embodiment of the disclosure has the advantages that the capacitors in different areas can be used for realizing different functions, and the integration level of the semiconductor device is improved.

Inventors

• YU HUALIANG
• ZONG HUI
• XING YANZHAO
• FENG WEI
• WU XIAOXIAN
• HAN ZHIHAO

Assignees

• 长鑫科技集团股份有限公司

Dates

Publication Date

20260512

Application Date

20241111

Claims (17)

1. 1. A semiconductor device, comprising: a first region and a second region; The active areas are arranged in the first area and comprise a first connecting end and a second connecting end; A plurality of first capacitors, each of the first capacitors being disposed in the first region, each of the first capacitors including a first upper electrode and a first lower electrode, the first lower electrode of each of the first capacitors being connected to each of the first connection terminals; a plurality of second capacitors, each of the second capacitors being disposed in the second region, each of the second capacitors including a second upper electrode and a second lower electrode; a plurality of first bonding pads, wherein the first bonding pads are arranged in the first area, and at least one first bonding pad is connected with the second connecting end of at least one active area; And a plurality of second bonding pads, wherein the second bonding pads are arranged in the second area, and at least one second bonding pad is connected with the second lower electrode of at least one second capacitor.
2. 2. The semiconductor device according to claim 1, wherein the first connection terminals of the active regions are arranged to be spaced apart from each other in a first direction and in a second direction, the second connection terminals of the active regions are isolated from each other in the first direction, and the second connection terminals of the active regions are connected to each other in the second direction.
3. 3. The semiconductor device according to claim 2, further comprising a first interconnect structure located in the first region and a second interconnect structure located in the second region, the first interconnect structure being disposed between each of the second connection terminals of each of the active regions and each of the first bonding pads, connecting each of the second connection terminals and each of the first bonding pads, the second interconnect structure being disposed between each of the second lower electrodes of each of the second capacitors and each of the second bonding pads, connecting each of the second lower electrodes and each of the second bonding pads.
4. 4. The semiconductor device of claim 3, further comprising a first combination of dielectric layers in the first region and a second combination of dielectric layers in the second region, the first combination of dielectric layers including a first isolation dielectric layer and the second combination of dielectric layers including a second isolation dielectric layer, the first isolation dielectric layer being disposed between the second connection terminals arranged in the first direction, the second isolation dielectric layer being disposed between the second interconnect structures.
5. 5. The semiconductor device of claim 4, wherein the first dielectric layer combination further comprises a first dielectric layer, the second dielectric layer combination further comprises a second dielectric layer, the first dielectric layer is disposed between the first connection terminals, and the second dielectric layer is disposed between the second lower electrodes of the second capacitors.
6. 6. The semiconductor device of claim 1, wherein the second region further comprises a common connection terminal to which the second lower electrode of each of the second capacitors is connected, the common connection terminal being connected to at least one of the second bond pads.
7. 7. The semiconductor device of claim 6, further comprising a second interconnect structure located in the second region, the second interconnect structure disposed between the common connection terminal and the second bond pad, connecting the common connection terminal and the second bond pad.
8. 8. A method of manufacturing a semiconductor device, comprising: providing a substrate, wherein the substrate is provided with a first area and a second area; Patterning a portion of the substrate to form a plurality of active regions in the first region, each of the active regions including a first connection terminal and a second connection terminal; Forming a plurality of first capacitors and a plurality of second capacitors in the first region and the second region respectively, wherein each first capacitor comprises a first upper electrode and a first lower electrode, the first lower electrode of each first capacitor is connected with each first connecting end, and each second capacitor comprises a second upper electrode and a second lower electrode; Removing the unpatterned portion of the substrate; And forming a plurality of first bonding pads in the first region and a plurality of second bonding pads in the second region, wherein at least one first bonding pad is connected with the second connection end of at least one active region, and at least one second bonding pad is connected with the second lower electrode of at least one second capacitor.
9. 9. The method for manufacturing a semiconductor device according to claim 8, wherein forming a plurality of active regions in the first region comprises: And patterning the substrate, forming a plurality of active areas extending along a third direction in the first area, wherein each active area comprises a first connecting end and a second connecting end which are arranged along the third direction, the first connecting ends of each active area are arranged at intervals in the first direction and in the second direction, and the second connecting ends of each active area are connected with each other in the first direction and the second direction.
10. 10. The method of manufacturing a semiconductor device according to claim 9, wherein patterning the substrate forms each of the active regions, a first groove is formed between each of the first connection terminals, and a second groove is formed between each of the second connection terminals in the second direction; Patterning a portion of the substrate of the first region to form each of the active regions, the portion of the substrate of the second region also being patterned, forming a third recess in the substrate of the second region; and forming a first insulating medium layer and a first isolating medium layer in the first groove and the second groove respectively, and forming a second isolating medium layer in the third groove.
11. 11. The method for manufacturing a semiconductor device according to claim 10, wherein after filling the first insulating dielectric layer, and the second insulating dielectric layer, a second insulating dielectric layer is formed over the second insulating dielectric layer, and wherein after forming the first insulating dielectric layer and the second insulating dielectric layer, the first capacitor and the second capacitor are formed.
12. 12. The method of manufacturing a semiconductor device according to claim 11, further comprising forming a common connection terminal in the second insulating dielectric layer, the common connection terminal being connected to the second lower electrode of at least one of the second capacitors, before forming the first capacitor and the second capacitor.
13. 13. The method of manufacturing a semiconductor device according to claim 10, wherein removing the unpatterned portion of the substrate comprises thinning the unpatterned portion of the substrate such that the second connection terminals of the active regions are isolated from each other in the first direction, the second connection terminals of the active regions remain connected to each other in the second direction while the second connection terminals, the surface of the first isolation dielectric layer, and the surface of the second isolation dielectric layer are exposed; After removing the unpatterned part of the substrate, forming a first sacrificial layer on the exposed surfaces of the second connection ends, the first isolation dielectric layer and the second isolation dielectric layer; After the first sacrificial layer is formed, performing a laser annealing process to activate each second connection end; And after activating each second connection end, removing the first sacrificial layer, and forming the first bonding pad and the second bonding pad in the first area and the second area respectively.
14. 14. The method of manufacturing a semiconductor device according to claim 13, wherein a first interconnect structure connected to each of the second connection terminals and a second interconnect structure connected to each of the second lower electrodes are formed before the first bonding pad and the second bonding pad are formed.
15. 15. The method for manufacturing a semiconductor device according to claim 13, wherein a thickness of the first sacrificial layer is one-fourth of a wavelength of laser light employed in the laser annealing process.
16. 16. The method of manufacturing a semiconductor device according to claim 13, wherein an ion implantation process is performed on each of the exposed second connection terminals before the first sacrificial layer is formed.
17. 17. The method for manufacturing a semiconductor device according to claim 8, wherein the second capacitor is formed in the second region while the first capacitor is formed in the first region.

Description

Semiconductor device and method for manufacturing the same Technical Field The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof. Background Transistors and capacitors are important components of DRAM devices in which the transistors function primarily as switches for controlling the charging and discharging of the capacitors, i.e., the writing and reading of data. Transistors typically comprise three key components, a source, a drain and a gate, the source and drain typically being doped by ion implantation techniques (e.g., arsenic or boron) to form n-type or p-type semiconductor regions, the implanted dopant atoms may initially be in an inactive state, i.e., they do not effectively participate in the conductivity process of the semiconductor, requiring dopant activation of the source and drain regions by a heat treatment process, commonly referred to as an activation anneal, at a temperature typically greater than 500 ℃. The H-K material acts as a dielectric layer for the capacitor, which can significantly reduce the physical size of the capacitor while maintaining or increasing the capacitance value of the capacitor. In general, H-K materials crystallize at about 500 ℃ to cause increased leakage, and in addition, since DRAM devices include a plurality of different regions, there are differences in pattern composition among the different regions, and the differences in pattern composition also cause local thermal stress due to high temperature, thereby causing product defects and affecting the production yield. Disclosure of Invention Embodiments of the present disclosure provide a semiconductor device having a higher integration level and a method of manufacturing the same. The problems to be solved by the technical spirit of the present disclosure are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. Some embodiments of the present disclosure provide a semiconductor device including a first region and a second region, a plurality of active regions each disposed in the first region, each active region including a first connection terminal and a second connection terminal, a plurality of first capacitors each disposed in the first region, each first capacitor including a first upper electrode and a first lower electrode, each first capacitor having a first lower electrode connected to each first connection terminal, a plurality of second capacitors each disposed in the second region, each second capacitor including a second upper electrode and a second lower electrode, a plurality of first bonding pads disposed in the first region, at least one first bonding pad connected to the second connection terminal of at least one active region, and a plurality of second bonding pads disposed in the second region, at least one second bonding pad connected to the second lower electrode of at least one second capacitor. In some embodiments, the first connection terminals of the active regions are spaced apart from each other in the first direction and in the second direction, the second connection terminals of the active regions are isolated from each other in the first direction, and the second connection terminals of the active regions are connected to each other in the second direction. In some embodiments, the first interconnect structure is disposed between each second connection end of each active region and each first bonding pad to connect each second connection end to each first bonding pad, and the second interconnect structure is disposed between each second bottom electrode of each second capacitor and each second bonding pad to connect each second bottom electrode to each second bonding pad. In some embodiments, the first dielectric layer assembly includes a first isolation dielectric layer, the second dielectric layer assembly includes a second isolation dielectric layer, the first isolation dielectric layer is disposed between the second connection ends arranged in the first direction, and the second isolation dielectric layer is disposed between the second interconnection structures. In some embodiments, the first dielectric layer combination further includes a first dielectric layer, the second dielectric layer combination further includes a second dielectric layer, the first dielectric layer is disposed between the first connection terminals, and the second dielectric layer is disposed between the second lower electrodes of the second capacitors. In some embodiments, the second region further includes a common connection terminal to which the second lower electrode of each second capacitor is connected, the common connection terminal being connected to at least one second bond pad. In some embodiments, a second interconnect structure is disposed in the second region, the second inter