CN-122028411-A - Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

A semiconductor device comprises a plurality of layers of memory cell arrays stacked in a direction perpendicular to a substrate, wherein each memory cell array comprises at least one column of memory cells, a plurality of vertically extending bit lines, a plurality of word lines extending in a second direction, each memory cell comprises a transistor and a semiconductor layer connected with the first electrode, the first electrode forms a cylindrical structure with an opening direction facing away from the semiconductor layer, the semiconductor layer surrounds the word line, the dimension of a surface of the semiconductor layer, facing the bit line, in the second direction is larger than the dimension of the bit line, in the second direction, and the semiconductor layer covers the surface of the first electrode, facing the semiconductor layer. According to the scheme provided by the embodiment of the disclosure, the semiconductor layer is larger in size along the second direction, so that the channel width is larger, and the on-state current of the transistor is improved.

Inventors

• WANG TUN
• FENG HONGLEI
• WANG XIANGSHENG
• WANG GUILEI
• ZHAO CHAO

Assignees

• 北京超弦存储器研究院

Dates

Publication Date

20260512

Application Date

20241112

Claims (15)

1. 1. A semiconductor device includes a multi-layered memory cell array stacked in a direction perpendicular to a substrate, the memory cell array including at least one column of a plurality of memory cells distributed in a second direction; A plurality of bit lines extending along a direction perpendicular to the substrate through the memory cells of different layers; A plurality of word lines distributed in different layers, wherein the word lines and the bit lines are distributed along a first direction, and the word lines extend along a second direction, and the first direction and the second direction are parallel to the substrate and are crossed; The memory cell comprises a transistor and a semiconductor layer connected with the first electrode, wherein the first electrode is arranged on one side of the semiconductor layer, which is away from the bit line, the first electrode forms a cylindrical structure, which is away from the semiconductor layer in the opening direction, a plurality of semiconductor layers of a plurality of transistors in the same column encircle the same word line, a plurality of semiconductor layers of a plurality of transistors in the same column are distributed at intervals along a second direction, the side wall, facing the bit line, of the semiconductor layer is perpendicular to the substrate, is connected with the bit line, the dimension of the surface, facing the bit line, of the semiconductor layer along the second direction is larger than the dimension of the bit line along the second direction, and the semiconductor layer covers the surface, facing the semiconductor layer, of the first electrode.
2. 2. The semiconductor device according to claim 1, further comprising a seventh insulating layer including a first sub-portion penetrating the multilayer, which is provided between bit lines adjacent in the second direction and extends in a direction perpendicular to the substrate, a second sub-portion penetrating the multilayer, which is provided between first electrodes adjacent in the second direction and extends in a direction perpendicular to the substrate, a third sub-portion provided at a side of the word line facing away from the substrate and not surrounded by the semiconductor layer, and a region of the word line facing toward the substrate and not surrounded by the semiconductor layer, and the third sub-portion filling a region between regions of the word line adjacent in the direction perpendicular to the substrate not surrounded by the semiconductor layer, the first sub-portion, the second sub-portion, and the third sub-portion being connected to form an integrated structure, the first sub-portion being connected to the word line facing toward the bit line side, and the second sub-portion being connected to the word line facing away from the bit line side.
3. 3. The semiconductor device according to claim 1, further comprising a third insulating layer and a fifth insulating layer filled between regions surrounded by the semiconductor layer along word lines adjacent in a direction perpendicular to a substrate, the third insulating layer and the fifth insulating layer being distributed along a first direction, the third insulating layer being provided on a side of the fifth insulating layer facing away from the bit line, and the third insulating layer forming a convex structure facing the bit line, the fifth insulating layer forming a concave structure on a side facing away from the bit line, the fifth insulating layer being connected to the bit line.
4. 4. The semiconductor device according to claim 1, wherein a distance of two semiconductor layers of two transistors adjacent in the second direction is larger on a side facing away from the bit line than on a side facing toward the bit line.
5. 5. The semiconductor device according to claim 1, further comprising an eleventh insulating layer provided between bit lines adjacent in the second direction and extending in a direction perpendicular to the substrate through the plurality of layers, and an eighth insulating layer provided between the eleventh insulating layer and the bit lines and extending in a direction perpendicular to the substrate through the plurality of layers; And a twelfth insulating layer including a fourth sub-portion which is distributed between the first electrodes adjacent in the second direction and extends in a direction perpendicular to the substrate and penetrates through the plurality of layers, and a fifth sub-portion which fills a region between regions of the word line adjacent in the direction perpendicular to the substrate, which are not surrounded by the semiconductor layer, the fourth sub-portion and the fifth sub-portion being connected to form an integrated structure, the eleventh insulating layer and the twelfth insulating layer being non-integrated.
6. 6. The semiconductor device according to claim 5, wherein the fourth sub-portion is arranged on an outer side wall of the first electrode extending in a direction perpendicular to the substrate and continuously extends from a bottom wall side of the outer side wall close to the tubular structure to a bottom wall side away from the tubular structure, and the fourth sub-portion includes a first portion and a second portion distributed in a first direction, the second portion is provided on a side of the first portion facing the word line, and a maximum dimension of the second portion in the second direction is larger than a maximum dimension of the first portion in the second direction.
7. 7. The semiconductor device according to claim 5, wherein a distance between two semiconductor layers adjacent in the second direction on a side away from the substrate or a side toward the substrate gradually decreases in a direction toward the bit line.
8. 8. The semiconductor device according to claim 1, wherein the transistor further includes a gate insulating layer provided between the semiconductor layer and the word line around the word line, the plurality of gate insulating layers of the plurality of transistors of the same column distributed in the second direction of the same layer are connected to form a unitary structure on a substrate-facing side and are disconnected on the bit line-facing side and the bit line-facing side, or the plurality of gate insulating layers of the plurality of transistors of the same column distributed in the second direction of the same layer are connected to form a unitary structure on a substrate-facing side, a bit line-facing side.
9. 9. The semiconductor device according to any one of claims 1 to 8, wherein the memory cell further includes a capacitor, the capacitor and the transistor of the same memory cell are distributed in the first direction, the capacitor includes a dielectric layer and a second capacitance electrode, the dielectric layer is disposed between the first electrode and the second capacitance electrode, the second capacitance electrode fills a cylindrical structure formed by the first electrode and is distributed on a side of the first electrode facing away from the substrate, a side facing toward the substrate, and an outer sidewall perpendicular to the substrate.
10. 10. The semiconductor device according to claim 9, wherein a plurality of second capacitor electrodes of the plurality of capacitors adjacent in the second direction are connected to form a unitary structure, and the unitary structure formed by the connection of the plurality of second capacitor electrodes fills a region between the first electrodes adjacent in the second direction, or the unitary structure formed by the connection of the plurality of second capacitor electrodes forms a recess having an opening direction toward the word line between the first electrodes adjacent in the second direction.
11. 11. A method of manufacturing a semiconductor device, comprising: forming a stacked structure including a plurality of first insulating layers and first sacrificial layers alternately disposed on a substrate; Forming a first trench penetrating the stacked structure in a direction perpendicular to the substrate and extending in a second direction, etching the first sacrificial layer in a direction parallel to the substrate based on the first trench, forming a first lateral trench; Forming a plurality of first holes penetrating through the second insulating layer along the direction perpendicular to the substrate and a plurality of third holes penetrating through the stacked structure along the direction perpendicular to the substrate, wherein the first holes are distributed at intervals along the second direction, the third holes are arranged on one side of the first isolating layer, which is away from the first groove, the side walls of the first holes expose the first isolating layer, the side walls of the third holes expose the first isolating layer, and the first holes and the third holes are distributed along the first direction; Forming a fourth hole penetrating through the stacked structure along the direction perpendicular to the substrate between the third holes adjacent along the second direction, wherein the side wall of the fourth hole does not expose the first isolation layer and exposes the first dummy layer; Forming a plurality of second holes penetrating through the second insulating layer along the direction perpendicular to the substrate between adjacent first holes along the second direction, wherein the side walls of the second holes expose the first insulating layer, and etching the first insulating layer along the direction parallel to the substrate based on the second holes so that the first insulating layer is broken into a plurality of sections distributed at intervals along the second direction; Etching to remove the first dummy layer in the first hole and the third hole, and etching the first sacrificial layer along the direction parallel to the substrate based on the first hole and the third hole to form a channel extending along the second direction; forming a semiconductor structure layer, a gate insulating structure layer and a word line in the channel in sequence, wherein the gate insulating structure layer and the semiconductor structure layer encircle the word line in sequence, the word line fills the channel, and the semiconductor structure layer is disconnected into a plurality of sections on one side facing the bit line and one side facing away from the bit line; And removing the first isolation layer by etching based on the first hole and the third hole, wherein the semiconductor structure layer exposed by etching faces to one side of the substrate and one side of the semiconductor structure layer away from the substrate, so that the semiconductor structure layer breaks into a plurality of sections distributed at intervals along the second direction on one side of the semiconductor structure layer facing to the substrate and one side of the semiconductor structure layer away from the substrate.
12. 12. The method of manufacturing a semiconductor device according to claim 11, wherein after etching the exposed semiconductor construction layer toward the substrate side and away from the substrate side, further comprising: the method comprises the steps of exposing the inner wall of a first electrode, forming a first transverse groove for filling the first electrode and an outer side wall covering the exposed side of the first electrode facing the substrate and the side facing away from the substrate, and forming a second capacitor electrode perpendicular to the outer side wall of the substrate, wherein the outer side wall of the first electrode facing the substrate and the side facing away from the substrate is perpendicular to the outer side wall of the substrate.
13. 13. A method of manufacturing a semiconductor device, comprising: forming a stacked structure including a plurality of first insulating layers and first sacrificial layers alternately disposed on a substrate; forming a plurality of fifth holes which penetrate through the stacked structure along the direction perpendicular to the substrate and are distributed at intervals along a second direction; Forming a second trench penetrating the stacked structure in a direction perpendicular to the substrate and extending in a second direction, wherein the second trench and the fifth hole are distributed at intervals in a first direction, forming a first barrier layer covering the bottom wall and the side wall of the fifth hole and a fourth dummy layer filling the fifth hole, etching the first sacrificial layer based on the second trench in a direction parallel to the substrate to form a second transverse trench, forming a second isolation layer filling the second transverse trench, and an eighth insulating layer filling the second trench, wherein the first direction and the second direction are parallel to the substrate and are intersected; Forming a third groove penetrating through the stacking structure along the direction perpendicular to the substrate and extending along a second direction, wherein the third groove is arranged on one side of the fifth hole away from the second groove; etching the first sacrificial layer along the direction parallel to the substrate based on the third groove to form a third transverse groove, wherein the third transverse groove comprises a first transverse groove arranged between adjacent first barrier layers; Forming a plurality of sixth holes penetrating through the eighth insulating layer along a direction perpendicular to the substrate, wherein the plurality of sixth holes are distributed at intervals along the second direction, and the side walls of the sixth holes are exposed out of the second isolation layer; Forming a plurality of seventh holes penetrating through the eighth insulating layer along the direction perpendicular to the substrate between the sixth holes adjacent along the second direction, wherein the side walls of the seventh holes expose the second isolation layer and do not expose the bit lines, and removing the first sacrificial layer along the direction parallel to the substrate based on the seventh holes in an etching way to form channels extending along the second direction; Etching the fourth dummy layer and the first barrier layer until the second isolation layer is exposed, removing the second isolation layer by etching, and breaking the semiconductor structure layer exposed by etching into a plurality of sections distributed at intervals along a second direction, wherein the sections are away from one side of the bit line, one side of the semiconductor structure layer faces towards the substrate and one side of the semiconductor structure layer faces away from the substrate.
14. 14. The method of manufacturing a semiconductor device according to claim 13, wherein after the channel sequentially forms the semiconductor structure layer, the gate insulating structure layer, and the word line, etching the fourth dummy layer and the first barrier layer until the second isolation layer is exposed, further comprising: Exposing the inner wall of the first electrode, the outer side wall of the first electrode on the side facing the substrate and the side facing away from the substrate, etching the first barrier layer and reserving the first barrier layer on the side facing the bit line, and exposing the outer side wall of the first electrode perpendicular to the substrate; and forming a first transverse groove for filling the first electrode, and a second capacitor electrode which covers the exposed side of the first electrode facing the substrate and the exposed side of the first electrode facing away from the substrate, wherein the first electrode is perpendicular to the outer side wall of the substrate.
15. 15. An electronic apparatus comprising the semiconductor device according to any one of claims 1 to 10, or a semiconductor device formed according to the method for manufacturing a semiconductor device according to any one of claims 11 to 14.

Description

Semiconductor device, manufacturing method thereof and electronic equipment Technical Field Embodiments of the present disclosure relate to device design and fabrication thereof, and more particularly to a semiconductor device, a fabrication method thereof, and an electronic device. Background With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing, so that any minor differences in process production may affect the performance of the devices. In order to reduce the cost of the product as much as possible, it is desirable to make as many device cells as possible on a limited substrate. Since moore's law emerged, various semiconductor structural designs and process optimizations have been proposed in the industry to meet the needs of people for current products. Disclosure of Invention The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims. The application provides a semiconductor device, a manufacturing method thereof, an electronic device and a method for manufacturing the semiconductor device. The application provides a semiconductor device, which comprises a plurality of layers of memory cell arrays stacked along a direction vertical to a substrate, wherein each memory cell array comprises at least one column of a plurality of memory cells distributed along a second direction; A plurality of bit lines extending along a direction perpendicular to the substrate through the memory cells of different layers; A plurality of word lines distributed in different layers, wherein the word lines and the bit lines are distributed along a first direction, and the word lines extend along a second direction, and the first direction and the second direction are parallel to the substrate and are crossed; The memory cell comprises a transistor and a semiconductor layer connected with the first electrode, wherein the first electrode is arranged on one side of the semiconductor layer, which is away from the bit line, the first electrode forms a cylindrical structure, which is away from the semiconductor layer in the opening direction, a plurality of semiconductor layers of a plurality of transistors in the same column encircle the same word line, a plurality of semiconductor layers of a plurality of transistors in the same column are distributed at intervals along a second direction, the side wall, facing the bit line, of the semiconductor layer is perpendicular to the substrate, is connected with the bit line, the dimension of the surface, facing the bit line, of the semiconductor layer along the second direction is larger than the dimension of the bit line along the second direction, and the semiconductor layer covers the surface, facing the semiconductor layer, of the first electrode. In some embodiments, the semiconductor device further includes a seventh insulating layer including a first sub-portion extending through the layers disposed between bit lines adjacent in the second direction and extending perpendicular to the substrate direction, a second sub-portion extending through the layers disposed between first electrodes adjacent in the second direction and extending perpendicular to the substrate direction, a third sub-portion disposed on a side of the word line facing away from the substrate and not surrounded by the semiconductor layer, and a region of the word line facing toward the substrate and not surrounded by the semiconductor layer, and the third sub-portion fills a region between regions of the word line adjacent in the perpendicular to the substrate direction not surrounded by the semiconductor layer, the first, second, and third sub-portions being connected to form an integral structure, the first sub-portion being connected to the word line facing toward the bit line, the second sub-portion being connected to the word line facing away from the bit line side. In some embodiments, the semiconductor device further includes a third insulating layer and a fifth insulating layer filled between regions surrounded by the semiconductor layer along adjacent word lines perpendicular to the substrate direction, the third insulating layer and the fifth insulating layer being distributed along a first direction, the third insulating layer being disposed on a side of the fifth insulating layer facing away from the bit line, and the third insulating layer forming a convex structure facing toward the bit line, the fifth insulating layer forming a concave structure on a side facing away from the bit line, the fifth insulating layer being connected to the bit line. In some embodiments, the distance of the two semiconductor layers of two transistors adjacent in the second direction is greater on the side facing away from the bit line than on the side facing toward the bit line. In some embodiments, the semiconduct