CN-122028413-A - Three-dimensional semiconductor device and method of manufacturing the same

Abstract

The present inventive concept relates to a three-dimensional semiconductor device and a method of manufacturing the same. The three-dimensional semiconductor device may include semiconductor patterns on a substrate, the semiconductor patterns extending in a first direction parallel to a lower surface of the substrate, spaced apart from each other in a vertical direction perpendicular to the lower surface of the substrate, word lines respectively surrounding the semiconductor patterns, each word line extending in a second direction parallel to the lower surface of the substrate and orthogonal to the first direction, a lower insulating layer adjacent to an end of the first group of semiconductor patterns, bit lines disposed on the lower insulating layer and adjacent to an end of the second group of semiconductor patterns, and separation insulating patterns penetrating at least a portion of the lower insulating layer. The separation insulating pattern may have a shape tapered toward the substrate.

Inventors

• JIN YUCHEN
• JIN YOUZHE
• JIN HUIBIN
• WU GUIHUAN
• ZHANG YINSHUO
• CUI ZHIXUN

Assignees

• 三星电子株式会社

Dates

Publication Date

20260512

Application Date

20250701

Priority Date

20241112

Claims (20)

1. 1. A three-dimensional semiconductor device comprising: semiconductor patterns disposed on a substrate, extending in a first direction parallel to a lower surface of the substrate, and spaced apart from each other in a vertical direction perpendicular to the lower surface of the substrate; word lines extending in a second direction parallel to the lower surface of the substrate and orthogonal to the first direction, respectively surrounding the semiconductor patterns; a lower insulating layer disposed adjacent to an end of the first group of semiconductor patterns; Bit lines disposed on the lower insulating layer and adjacent to ends of the second group of the semiconductor patterns, and Separating the insulating pattern to penetrate at least a portion of the lower insulating layer, Wherein the separation insulating pattern has a shape tapered toward the substrate.
2. 2. The three-dimensional semiconductor device of claim 1, wherein the lower insulating layer and the separation insulating pattern comprise different materials.
3. 3. The three-dimensional semiconductor device according to claim 1, wherein an uppermost surface of the separation insulating pattern is disposed at a level higher than a recessed surface of the lower insulating layer.
4. 4. The three-dimensional semiconductor device according to claim 1, wherein an uppermost surface of the separation insulating pattern is disposed at a higher level than a lowermost surface of the bit line.
5. 5. The three-dimensional semiconductor device of claim 1, wherein at least one of the first set of semiconductor patterns is disposed at a level lower than a lowermost surface of the bit line.
6. 6. The three-dimensional semiconductor device according to claim 1, wherein a lowermost portion of the separation insulating pattern is provided in the lower insulating layer.
7. 7. The three-dimensional semiconductor device according to claim 1, wherein a lowermost portion of the separation insulating pattern is provided in the substrate.
8. 8. The three-dimensional semiconductor device according to claim 1, wherein a width of the separation insulating pattern in the first direction increases in the vertical direction in a direction away from the substrate.
9. 9. A three-dimensional semiconductor device comprising: semiconductor patterns disposed on a substrate, extending in a first direction parallel to a lower surface of the substrate, and spaced apart from each other in a vertical direction perpendicular to the lower surface of the substrate; word lines extending in a second direction parallel to the lower surface of the substrate and orthogonal to the first direction, respectively surrounding the semiconductor patterns; a lower insulating layer disposed adjacent to an end portion of the first group of the semiconductor patterns; Bit lines disposed on the lower insulating layer and adjacent to end portions of the second group of the semiconductor patterns, and Separating the insulating pattern to penetrate at least a portion of the lower insulating layer, Wherein an uppermost surface of the separation insulating pattern is disposed at a level higher than a recessed surface of the lower insulating layer.
10. 10. The three-dimensional semiconductor device of claim 9, wherein the lower insulating layer and the separation insulating pattern comprise different materials.
11. 11. The three-dimensional semiconductor device according to claim 9, wherein the separation insulating pattern has a V shape when viewed in a cross-sectional view.
12. 12. The three-dimensional semiconductor device according to claim 9, wherein a width of the separation insulating pattern in the first direction increases in the vertical direction in a direction away from the substrate.
13. 13. The three-dimensional semiconductor device according to claim 9, wherein the uppermost surface of the separation insulating pattern is disposed at a higher level than a lowermost surface of the bit line.
14. 14. The three-dimensional semiconductor device of claim 9, wherein at least one of the first set of semiconductor patterns is disposed at a level below a lowermost surface of the bit line.
15. 15. The three-dimensional semiconductor device according to claim 9, wherein a lowermost portion of the separation insulating pattern is provided in the substrate.
16. 16. A three-dimensional semiconductor device comprising: A semiconductor pattern disposed on a substrate, extending in a first direction parallel to a lower surface of the substrate, spaced apart from each other in a vertical direction perpendicular to the lower surface of the substrate, each of the semiconductor patterns having a first end and a second end opposite to each other in the first direction; word lines extending in a second direction parallel to the lower surface of the substrate and orthogonal to the first direction, respectively surrounding the semiconductor patterns; Gate insulating patterns respectively disposed between the semiconductor patterns and the word lines; A data storage pattern connected to the first end of the semiconductor pattern, extending in the vertical direction; a lower insulating layer disposed adjacent to the second ends of the first group of semiconductor patterns; bit lines disposed on the lower insulating layer and adjacent to the second ends of the second group of semiconductor patterns, and Separating the insulating pattern to penetrate at least a portion of the lower insulating layer, Wherein a width of the separation insulating pattern in the first direction continuously varies in the vertical direction.
17. 17. The three-dimensional semiconductor device of claim 16, wherein the lower insulating layer and the separation insulating pattern comprise different materials.
18. 18. The three-dimensional semiconductor device according to claim 16, wherein an uppermost surface of the separation insulating pattern is disposed at a level higher than a recessed surface of the lower insulating layer.
19. 19. The three-dimensional semiconductor device of claim 16, wherein at least one of the first set of semiconductor patterns is disposed at a level below a lowermost surface of the bit line.
20. 20. The three-dimensional semiconductor device according to claim 16, wherein a lowermost portion of the separation insulating pattern is provided in the substrate.

Description

Three-dimensional semiconductor device and method of manufacturing the same Technical Field The present inventive concept relates to a three-dimensional semiconductor device and a method of manufacturing the same, and more particularly, to a three-dimensional semiconductor device having improved reliability and integration. Background Semiconductor devices are widely used in the electronics industry due to their small size, multi-functional characteristics, and/or low manufacturing costs. The semiconductor device may be classified as a semiconductor memory device for storing logic data, a semiconductor logic device for processing logic data, or a hybrid semiconductor device having both the function of the semiconductor memory device and the function of the semiconductor logic device. As high speed and/or low power electronics have been demanded, high speed and/or low voltage semiconductor devices used therein have also been demanded, and highly integrated semiconductor devices have been demanded to meet these demands. However, as the integration density of semiconductor devices increases, there is a possibility that the electrical characteristics and yield of the semiconductor devices may decrease. Accordingly, various researches have been conducted on techniques for improving the electrical characteristics and yield of semiconductor devices. Disclosure of Invention An object of the inventive concept is to provide a three-dimensional semiconductor device having improved electrical characteristics and reliability. The problems to be solved by the inventive concept are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. The three-dimensional semiconductor device according to some embodiments of the inventive concept may include semiconductor patterns disposed on a substrate, extending in a first direction parallel to a lower surface of the substrate, spaced apart from each other in a vertical direction perpendicular to the lower surface of the substrate, word lines respectively surrounding the semiconductor patterns, extending in a second direction parallel to the lower surface of the substrate and orthogonal to the first direction, a lower insulating layer disposed adjacent to ends of the first group of semiconductor patterns, bit lines disposed on the lower insulating layer and adjacent to ends of the second group of semiconductor patterns, and separation insulating patterns penetrating at least a portion of the lower insulating layer. The separation insulating pattern may have a shape tapered toward the substrate. The three-dimensional semiconductor device according to some embodiments of the inventive concept may include semiconductor patterns disposed on a substrate, extending in a first direction parallel to a lower surface of the substrate, spaced apart from each other in a vertical direction perpendicular to the lower surface of the substrate, word lines respectively surrounding the semiconductor patterns, extending in a second direction parallel to the lower surface of the substrate and orthogonal to the first direction, a lower insulating layer disposed adjacent to end portions of the first group of semiconductor patterns, bit lines disposed on the lower insulating layer and adjacent to end portions of the second group of semiconductor patterns, and separation insulating patterns penetrating at least a portion of the lower insulating layer. The uppermost surface of the separation insulating pattern is disposed at a level higher than the recessed surface of the lower insulating layer. The three-dimensional semiconductor device according to some embodiments of the inventive concept may include semiconductor patterns disposed on a substrate, extending in a first direction parallel to a lower surface of the substrate, spaced apart from each other in a vertical direction perpendicular to the lower surface of the substrate, each of the semiconductor patterns having first and second ends opposite to each other in the first direction, word lines respectively surrounding the semiconductor patterns, extending in a second direction parallel to the lower surface of the substrate and orthogonal to the first direction, gate insulating patterns respectively disposed between the semiconductor patterns and the word lines, data storage patterns connected to the first ends of the semiconductor patterns, extending in the vertical direction, a lower insulating layer disposed adjacent to the second ends of the first group of semiconductor patterns, bit lines disposed on the lower insulating layer and adjacent to the second ends of the second group of semiconductor patterns, and separation insulating patterns penetrating at least a portion of the lower insulating layer. The width of the separation insulating pattern in the first direction continuously varies in the vertical direction. Drawings Example embodimen