CN-122028414-A - Semiconductor memory device having a memory cell with a memory cell having a memory cell with a memory cell

Abstract

A semiconductor memory device includes a plurality of memory cell blocks including a plurality of vertical channel transistors, and a boundary region surrounding each of the plurality of memory cell blocks in a plan view. The semiconductor memory device further includes a first device isolation layer located in the boundary region and facing the plurality of vertical channel transistors in a first horizontal direction, and a second device isolation layer spaced apart from the plurality of vertical channel transistors in the first horizontal direction, wherein the first device isolation layer is located between the second device isolation layer and the plurality of vertical channel transistors. The first device isolation layer includes a first portion, a second portion disposed on the first portion, and a stepped portion disposed on the first portion and extending in the first horizontal direction from an inner wall of the second portion to the second device isolation layer.

Inventors

• JIN CHENGXUN
• LI JUANZHEN
• JIANG XIUZHEN
• Jin Rongkuan
• JIN XIZHONG
• Cai Xizai

Assignees

• 三星电子株式会社

Dates

Publication Date

20260512

Application Date

20250814

Priority Date

20241112

Claims (20)

1. 1. A semiconductor memory device, the semiconductor memory device comprising: A plurality of memory cell blocks including a plurality of vertical channel transistors; a boundary region surrounding each of the plurality of memory cell blocks and configured to insulate each of the plurality of memory cell blocks from each other; a first device isolation layer located in the boundary region and facing the plurality of vertical channel transistors in a first horizontal direction, and A second device isolation layer spaced apart from the plurality of vertical channel transistors in the first horizontal direction, wherein the first device isolation layer is located between the second device isolation layer and the plurality of vertical channel transistors, Wherein the first device isolation layer includes a first portion, a second portion disposed on the first portion, and a step portion disposed on the first portion and extending in the first horizontal direction from an inner wall of the second portion to the second device isolation layer.
2. 2. The semiconductor memory device according to claim 1, wherein the step portion has an upper surface in contact with the second device isolation layer and an inner wall in contact with the second device isolation layer, and the upper surface and the inner wall are flat surfaces.
3. 3. The semiconductor memory device of claim 1, wherein the first device isolation layer and the second device isolation layer comprise different materials.
4. 4. The semiconductor memory device of claim 1, wherein the second device isolation layer comprises a first portion disposed on the first portion of the first device isolation layer and a second portion disposed on the first portion of the second device isolation layer.
5. 5. The semiconductor memory device according to claim 4, wherein, The lower surface of the second portion of the first device isolation layer and the lower surface of the first portion of the second device isolation layer lie in the same plane.
6. 6. The semiconductor memory device according to claim 1, wherein the step portion has an inner wall in contact with the second device isolation layer, and the inner wall is a curved surface.
7. 7. The semiconductor memory device of claim 1, wherein, Each of the plurality of vertical channel transistors includes: a back gate electrode extending in a second horizontal direction intersecting the first horizontal direction; a first channel structure and a second channel structure, the first channel structure and the second channel structure being arranged on opposite sides of the back gate electrode in the first horizontal direction; a word line spaced apart from a first side of the back gate electrode in the first horizontal direction, wherein the first channel structure is located between the word line and the back gate electrode; A back gate dielectric film between the first channel structure and the back gate electrode, and A gate dielectric film between the first channel structure and the word line, Wherein, the The bottom surface of the back gate dielectric film, the bottom surface of the gate dielectric film, and the lower surface of the first portion of the first device isolation layer lie in the same plane.
8. 8. The semiconductor memory device according to claim 7, wherein the back gate dielectric film covers a lower surface of the back gate electrode, and the gate dielectric film covers a lower surface of the word line.
9. 9. The semiconductor memory device of claim 7, comprising, for each back gate electrode, additional word lines spaced apart from a second side of the back gate electrode in the first horizontal direction to form conductive line groups, wherein each conductive line group is spaced apart from an adjacent conductive line group in the first horizontal direction by an isolation insulating pattern.
10. 10. The semiconductor memory device according to claim 9, wherein the isolation insulating pattern comprises a different material than the first device isolation layer.
11. 11. The semiconductor memory device according to claim 9, wherein the isolation insulating pattern comprises a same material as that of the first device isolation layer.
12. 12. A semiconductor memory device, the semiconductor memory device comprising: a plurality of conductive lines extending in a first horizontal direction and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction; A first interlayer insulating layer surrounding the plurality of conductive lines; A plurality of contact plugs arranged at positions spaced apart from the plurality of conductive lines in a vertical direction; a second interlayer insulating layer surrounding the plurality of contact plugs; a plurality of vertical channel transistors located between the plurality of conductive lines and the plurality of contact plugs, the plurality of vertical channel transistors including a plurality of channel structures, each of the plurality of channel structures being in contact with a respective one of the plurality of conductive lines and a respective one of the plurality of contact plugs; A first device isolation layer located between the first and second interlayer insulating layers and facing the plurality of vertical channel transistors in the first horizontal direction, and A second device isolation layer spaced apart from the plurality of vertical channel transistors in the first horizontal direction, wherein the first device isolation layer is located between the second device isolation layer and the plurality of vertical channel transistors, Wherein the first device isolation layer includes a first portion, a second portion located on the first portion, and a step portion located on the first portion and extending in the first horizontal direction from an inner wall of the second portion to the second device isolation layer.
13. 13. The semiconductor memory device according to claim 12, wherein the step portion has an upper surface in contact with the second device isolation layer and an inner wall in contact with the second device isolation layer, and the upper surface and the inner wall are flat surfaces.
14. 14. The semiconductor memory device of claim 12, wherein the second device isolation layer comprises a first portion located on the first portion of the first device isolation layer and a second portion located on the first portion of the second device isolation layer.
15. 15. The semiconductor memory device of claim 14, wherein, The lower surface of the second portion of the first device isolation layer and the lower surface of the first portion of the second device isolation layer lie in the same plane.
16. 16. The semiconductor memory device according to claim 12, wherein the step portion has an inner wall in contact with the second device isolation layer, and the inner wall is a curved surface.
17. 17. The semiconductor memory device of claim 12, wherein, Each of the plurality of vertical channel transistors includes: A back gate electrode extending in the second horizontal direction; a first channel structure and a second channel structure, the first channel structure and the second channel structure being arranged on opposite sides of the back gate electrode in the first horizontal direction; a word line spaced apart from a first side of the back gate electrode in the first horizontal direction, wherein the first channel structure is located between the word line and the back gate electrode; A back gate dielectric film between the first channel structure and the back gate electrode, and A gate dielectric film between the first channel structure and the word line, Wherein, the The bottom surface of the back gate dielectric film, the bottom surface of the gate dielectric film, and the lower surface of the first portion of the first device isolation layer lie in the same plane.
18. 18. The semiconductor memory device of claim 17, wherein the back gate dielectric film covers a lower surface of the back gate electrode and the gate dielectric film covers a lower surface of the word line.
19. 19. A semiconductor memory device, the semiconductor memory device comprising: A memory cell region including a plurality of memory cell blocks and a boundary region surrounding the plurality of memory cell blocks, and A peripheral circuit region surrounding the memory cell region, Wherein the semiconductor memory device further comprises: A plurality of vertical channel transistors arranged in each of the plurality of memory cell blocks; a first device isolation layer located in the boundary region and facing the plurality of vertical channel transistors in a first horizontal direction, and A second device isolation layer spaced apart from the plurality of vertical channel transistors in the first horizontal direction, wherein the first device isolation layer is located between the second device isolation layer and the plurality of vertical channel transistors, and Wherein the first device isolation layer includes a first portion, a second portion located on the first portion, and a step portion located on the first portion and extending in the first horizontal direction from an inner wall of the second portion to the second device isolation layer.
20. 20. The semiconductor memory device of claim 19, wherein the first device isolation layer comprises silicon nitride and the second device isolation layer comprises silicon oxide.

Description

Semiconductor memory device having a memory cell with a memory cell having a memory cell with a memory cell Technical Field The present disclosure relates to a semiconductor memory device and a method of manufacturing the same. Background The downsizing of semiconductor devices has recently been rapidly proceeding due to advances in electronic technology. A semiconductor memory device including a transistor having a vertical channel has been proposed as a structure that promotes miniaturization and high integration of memory cells. Disclosure of Invention The present disclosure describes a semiconductor memory device having improved structural reliability and a method of manufacturing the same. According to some embodiments, a semiconductor memory device is provided that includes a plurality of memory cell blocks including a plurality of vertical channel transistors, a boundary region surrounding each of the plurality of memory cell blocks in a plan view, a first device isolation layer located in the boundary region and facing the plurality of vertical channel transistors in a first horizontal direction, and a second device isolation layer spaced apart from the plurality of vertical channel transistors in the first horizontal direction, wherein the first device isolation layer is located between the plurality of vertical channel transistors and the second device isolation layer, wherein the first device isolation layer includes a first portion, a second portion disposed on the first portion, and a step portion disposed on the first portion and extending from an inner wall of the second portion to the second device isolation layer in the first horizontal direction. According to some embodiments, a semiconductor memory device is provided that includes a plurality of conductive lines extending longitudinally in a first horizontal direction and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction; the semiconductor device includes a plurality of conductive lines, a first interlayer insulating layer surrounding the plurality of conductive lines, a plurality of contact plugs arranged at positions spaced apart from the plurality of conductive lines in a vertical direction, a second interlayer insulating layer surrounding the plurality of contact plugs, a plurality of vertical channel transistors between the plurality of conductive lines and the plurality of contact plugs, the plurality of vertical channel transistors including a plurality of channel structures in contact with a selected one of the plurality of conductive lines and a selected one of the plurality of contact plugs, a first device isolation layer between the first interlayer insulating layer and the second interlayer insulating layer and facing the plurality of vertical channel transistors in the first horizontal direction, and a second device isolation layer between the plurality of vertical channel transistors in the first horizontal direction, wherein the first device isolation layer is spaced apart from the plurality of vertical channel transistors by a first device isolation layer, wherein the first device isolation layer is between the first device isolation layer and the first device isolation layer, the second device isolation layer includes a first device isolation layer, and a second device isolation layer, A second portion located on the first portion and a step portion located on the first portion and extending in the first horizontal direction from an inner wall of the second portion to the second device isolation layer. According to some embodiments, a semiconductor memory device is provided that includes a memory cell region including a plurality of memory cell blocks and a boundary region surrounding the plurality of memory cell blocks, and a peripheral circuit region surrounding the memory cell region, wherein the semiconductor memory device further includes a plurality of vertical channel transistors arranged in each of the plurality of memory cell blocks, a first device isolation layer located in the boundary region and facing the plurality of vertical channel transistors in a first horizontal direction, and a second device isolation layer spaced apart from the plurality of vertical channel transistors in the first horizontal direction, wherein the first device isolation layer is located between the second device isolation layer and the plurality of vertical channel transistors, and wherein the first device isolation layer includes a first portion, a second portion located on the first portion, and a step located on the first portion and extending from the first portion to the second inner wall in the first horizontal direction. Drawings Some embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: fig. 1 is a plan layout view schematically showing a semiconductor memory device according