CN-122028415-A - Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Abstract

A semiconductor device includes a substrate including a first active region, a word line intersecting the first active region and extending in a first direction, and a bit line intersecting the word line and extending in a second direction, wherein the bit line includes a first bit line conductive layer including a semiconductor material, a second bit line conductive layer on the first bit line conductive layer, a third bit line conductive layer on the second bit line conductive layer, and a fourth bit line conductive layer on the third bit line conductive layer, the fourth bit line conductive layer including a metal material, the third bit line conductive layer including a compound of the metal material and the first semiconductor material.

Inventors

• JIN HENGKUI
• JIN LIHUAN
• LI ZHIHUI
• Zhao Nanzhen

Assignees

• 三星电子株式会社

Dates

Publication Date

20260512

Application Date

20251110

Priority Date

20241111

Claims (20)

1. 1. A semiconductor device, comprising: A substrate comprising a first active region; A word line intersecting the first active region and extending in a first direction, and A bit line crossing the word line and extending in a second direction, Wherein the bit line includes: a first bit line conductive layer comprising a semiconductor material, A second bit line conductive layer on the first bit line conductive layer, A third bit line conductive layer on the second bit line conductive layer, and A fourth bit line conductive layer on the third bit line conductive layer, Wherein the fourth bit line conductive layer comprises a metal material, Wherein the third bit line conductive layer comprises a compound of the metal material and the first semiconductor material, and Wherein an atomic ratio of the metal material included in the third bit line conductive layer to the first semiconductor material is greater than 1:3 and less than 1:1.
2. 2. The semiconductor device according to claim 1, wherein a direction of stress applied to the fourth bit line conductive layer through the third bit line conductive layer is opposite to a direction of stress applied to the fourth bit line conductive layer through a plurality of layers between the substrate and the third bit line conductive layer.
3. 3. The semiconductor device according to claim 2, Wherein the plurality of layers are configured to apply compressive stress to the fourth bit line conductive layer, and Wherein the third bit line conductive layer is configured to relieve compressive stress applied to the fourth bit line conductive layer.
4. 4. The semiconductor device of claim 1, wherein a ratio of a thickness of the third bit line conductive layer to a thickness of the fourth bit line conductive layer is greater than 1:6 and less than 1:3.
5. 5. The semiconductor device according to claim 1, Wherein the bit line further comprises a fifth bit line conductive layer on the fourth bit line conductive layer, and Wherein the fifth bit line conductive layer comprises a compound of the metal material and a second semiconductor material.
6. 6. The semiconductor device of claim 5, wherein a ratio of a sum of thicknesses of the third bit line conductive layer and the fifth bit line conductive layer to a thickness of the fourth bit line conductive layer is greater than 1:6 and less than 1:3.
7. 7. The semiconductor device of claim 1, wherein the second bit line conductive layer comprises a different material than the first semiconductor material.
8. 8. The semiconductor device according to claim 1, Wherein the substrate includes a cell region and a peripheral circuit region surrounding the cell region, the cell region including the first active region, Wherein the peripheral circuit region includes a second active region, Wherein the semiconductor device includes a gate electrode intersecting the second active region and extending in the second direction, Wherein the gate electrode comprises a layer located in the same layer as the bit line, and Wherein the gate electrode comprises the same material as that of the bit line.
9. 9. The semiconductor device according to claim 8, wherein the gate electrode comprises: a first gate conductive layer in the same layer as the first bit line conductive layer; a second gate conductive layer on the first gate conductive layer and in the same layer as the second bit line conductive layer; A third gate conductive layer on the second gate conductive layer and in the same layer as the third bit line conductive layer, and A fourth gate conductive layer on the third gate conductive layer and in the same layer as the fourth bit line conductive layer.
10. 10. The semiconductor device according to claim 9, Wherein the first gate conductive layer comprises the same material as the first bit line conductive layer, Wherein the second gate conductive layer comprises the same material as the second bit line conductive layer, Wherein the third gate conductive layer comprises the same material as that of the third bit line conductive layer, and Wherein the fourth gate conductive layer comprises the same material as the fourth bit line conductive layer.
11. 11. A semiconductor device, comprising: A substrate comprising a first active region; A word line intersecting the first active region and extending in a first direction, and A bit line crossing the word line and extending in a second direction, Wherein the bit line includes: a first semiconductor layer comprising a semiconductor material; A first metal layer on the first semiconductor layer and including a metal material; A first interface layer between the first semiconductor layer and the first metal layer, and A first metal silicide layer covering a lower surface of the first metal layer, Wherein the first metal silicide layer comprises a metal material identical to that of the first metal layer, and Wherein the atomic number of silicon of the first metal silicide layer is greater than the atomic number of the metal material.
12. 12. The semiconductor device of claim 11, wherein an atomic ratio of a metal material included in the first metal silicide layer to silicon included in the first metal silicide layer is greater than 1:3 and less than 1:1.
13. 13. The semiconductor device of claim 11, wherein a thickness ratio of the first metal silicide layer to the first metal layer is greater than 1:6 and less than 1:3.
14. 14. The semiconductor device according to claim 11, Wherein the bit line comprises a second metal silicide layer covering the upper surface of the first metal layer, and Wherein the second metal silicide layer comprises a metal material identical to that of the first metal layer.
15. 15. The semiconductor device according to claim 11, Wherein the substrate includes a cell region and a peripheral circuit region surrounding the cell region, the cell region including the first active region, Wherein the peripheral circuit region includes a second active region, Wherein the semiconductor device includes a gate electrode intersecting the second active region and extending in the second direction, and Wherein the gate electrode includes a layer having the same material as that of the bit line.
16. 16. The semiconductor device according to claim 15, Wherein the gate electrode includes: A second semiconductor layer including the same material as that of the first semiconductor layer; A second metal layer including a metal material identical to that of the first metal layer; A second interface layer comprising the same material as the first interface layer, and A third metal silicide layer comprising the same material as the first metal silicide layer, Wherein the second metal layer is on the second semiconductor layer, Wherein the second interface layer is between the second semiconductor layer and the second metal layer, and Wherein the third metal silicide layer covers the lower surface of the second metal layer.
17. 17. The semiconductor device according to claim 16, Wherein the gate electrode further comprises a fourth metal silicide layer covering the upper surface of the second metal layer, and Wherein the fourth metal silicide layer comprises the same material as that of the third metal silicide layer.
18. 18. A semiconductor device, comprising: A substrate comprising an active region; a word line intersecting the active region and extending in a first direction, and A bit line crossing the word line and extending in a second direction, Wherein the bit line includes: a first bit line conductive layer comprising a semiconductor material; a second bit line conductive layer on the first bit line conductive layer; a third bit line conductive layer on the second bit line conductive layer, and A fourth bit line conductive layer on the third bit line conductive layer, Wherein the fourth bit line conductive layer comprises a metal material, Wherein the third bit line conductive layer comprises a compound of the metal material and the first semiconductor material, and Wherein the second bit line conductive layer comprises a material different from a material of the first semiconductor material.
19. 19. The semiconductor device of claim 18, wherein an atomic ratio of metal material to semiconductor material included in the third bit line conductive layer is greater than 1:3 and less than 1:1.
20. 20. The semiconductor device of claim 18, wherein a thickness ratio of the third bit line conductive layer to the fourth bit line conductive layer is greater than 1:6 and less than 1:3.

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips Cross Reference to Related Applications The present application claims priority from korean patent application No. 10-2024-0159559 filed at the korean intellectual property office on 11/2024, the contents of which are incorporated herein by reference in their entirety. Technical Field The present disclosure relates to a semiconductor device. Background A semiconductor is a material belonging to an intermediate region between a conductor and an insulator, and refers to a material that conducts electricity under predetermined conditions. With these semiconductor materials, various semiconductor devices, such as memory devices, can be manufactured. These semiconductor devices may be used in a variety of electronic devices. With the trend toward miniaturization and higher integration of electronic devices, it is required to finely form patterns constituting semiconductor devices. As the width of these fine patterns gradually decreases, the film stress increases, which may cause warpage of the semiconductor device. Disclosure of Invention The present disclosure relates generally to semiconductor devices that improve warpage problems by relieving film stress. According to some embodiments, the present disclosure relates to a semiconductor device including a substrate including a first active region, a word line intersecting the first active region and extending in a first direction, and a bit line intersecting the word line and extending in a second direction, wherein the bit line includes a first bit line conductive layer including a semiconductor material, a second bit line conductive layer on the first bit line conductive layer, a third bit line conductive layer on the second bit line conductive layer, and a fourth bit line conductive layer on the third bit line conductive layer, wherein the fourth bit line conductive layer includes a metal material, wherein the third bit line conductive layer includes a compound of the metal material and the first semiconductor material, and wherein an atomic ratio of the metal material included in the third bit line conductive layer to the first semiconductor material is greater than 1:3 and less than 1:1. According to some embodiments, the present disclosure relates to a semiconductor device including a substrate including a first active region, a word line crossing the first active region and extending in a first direction, and a bit line crossing the word line and extending in a second direction, wherein the bit line includes a first semiconductor layer including a semiconductor material, a first metal layer on the first semiconductor layer and including a metal material, a first interface layer between the first semiconductor layer and the first metal layer, and a first metal silicide layer covering a lower surface of the first metal layer, wherein the first metal silicide layer includes a metal material identical to a material of the first metal layer, and wherein an atomic number of silicon of the first metal silicide layer is greater than an atomic number of the metal material. According to some embodiments, the present disclosure relates to a semiconductor device comprising a substrate comprising an active region, a word line intersecting the active region and extending in a first direction, and a bit line intersecting the word line and extending in a second direction, wherein the bit line comprises a first bit line conductive layer comprising a semiconductor material, a second bit line conductive layer on the first bit line conductive layer, a third bit line conductive layer on the second bit line conductive layer, and a fourth bit line conductive layer on the third bit line conductive layer, wherein the fourth bit line conductive layer comprises a metal material, wherein the third bit line conductive layer comprises a compound of the metal material and the first semiconductor material, and wherein the second bit line conductive layer comprises a material different from the material of the first semiconductor material. According to some embodiments, the present disclosure relates to improving warpage problems by relieving film stress of semiconductor devices. Drawings Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. Fig. 1 is a schematic top plan view of an example of a semiconductor device according to some embodiments. Fig. 2 is an enlarged top plan view of R1 in fig. 1, according to some embodiments. Fig. 3 is an enlarged top plan view of R2 in fig. 1 according to some embodiments. Fig. 4 is a cross-sectional view taken along line A-A' of fig. 2, according to some embodiments. Fig. 5 is a cross-sectional view taken along line B-B' of fig. 2, according to some embodiments. Fig. 6 is an enlarged cross-sectional view of R3 in fig. 5, according to some embodiments. Fig. 7 is a cross-