CN-122028416-A - Semiconductor memory device having a memory cell with a memory cell having a memory cell with a memory cell

Abstract

The application provides a semiconductor memory device. The semiconductor memory device includes a substrate including a stacked structure defined by an isolation structure, a word line extending in a vertical direction and located at one side of the stacked structure, and a semiconductor layer located at the other side of the stacked structure and disposed opposite to the word line, wherein the semiconductor layer and the word line are in direct contact. The semiconductor memory device is used for achieving the effect of improving the data retention time.

Inventors

• YOSHIHIRO NAGAI

Assignees

• 福建省晋华集成电路有限公司

Dates

Publication Date

20260512

Application Date

20260120

Claims (16)

1. 1. A semiconductor memory device, comprising: A substrate on which a stacked structure defined by an isolation structure is provided; a word line extending in a vertical direction and located at one side of the stacked structure; A semiconductor layer located at the other side of the stacked structure and opposite to the word line; wherein the semiconductor layer and the word line are in direct contact.
2. 2. The semiconductor memory device according to claim 1, wherein the semiconductor layer extends in the vertical direction and directly contacts a portion of a sidewall of the stacked structure.
3. 3. The semiconductor memory device according to claim 1, wherein the stacked structure includes channel layers and insulating layers alternately arranged; each channel layer comprises a discontinuous first channel region and a discontinuous second channel region, and the first channel region and the second channel region are oppositely arranged at two sides of the word line.
4. 4. The semiconductor memory device according to claim 3, wherein the first channel region and the second channel region are each in direct contact with the semiconductor layer.
5. 5. The semiconductor memory device according to claim 4, wherein conductivity types of the first channel region, the second channel region, and the semiconductor layer are the same; the semiconductor layer has a dopant ion concentration less than a dopant ion concentration of the first channel region and less than a dopant ion concentration of the second channel region.
6. 6. The semiconductor memory device according to claim 5, wherein a conductivity type of the semiconductor layer is opposite to a conductivity type of the first channel region and opposite to a conductivity type of the second channel region; the semiconductor layer has a dopant ion concentration less than a dopant ion concentration of the first channel region and less than a dopant ion concentration of the second channel region.
7. 7. The semiconductor memory device according to any one of claims 3 to 6, wherein the word line fills a gap between adjacent ones of the insulating layers.
8. 8. The semiconductor memory device according to any one of claims 3 to 6, wherein the semiconductor layer fills a gap between adjacent ones of the insulating layers.
9. 9. The semiconductor memory device according to claim 8, wherein the semiconductor layer directly contacts a sidewall and a top surface of the insulating layer.
10. 10. A semiconductor memory device, comprising: A substrate, on which a stack structure defined by an isolation structure is provided, the stack structure including channel layers and insulating layers alternately arranged; a word line extending in a vertical direction and located at one side of the stacked structure; A semiconductor layer located at the other side of the stacked structure and opposite to the word line; The portion of the word line in direct contact with the insulating layer has a first thickness, and the portion of the word line in direct contact with the semiconductor layer has a second thickness, the second thickness being greater than the first thickness.
11. 11. The semiconductor memory device according to claim 10, wherein the semiconductor layer extends in the vertical direction and directly contacts a sidewall of the insulating layer.
12. 12. The semiconductor memory device according to claim 10, wherein each of the channel layers includes discontinuous first and second channel regions, the first and second channel regions being disposed opposite sides of the word line.
13. 13. The semiconductor memory device according to claim 12, wherein the first channel region and the second channel region are each in direct contact with the semiconductor layer.
14. 14. The semiconductor memory device according to claim 12, wherein conductivity types of the first channel region, the second channel region, and the semiconductor layer are the same; the semiconductor layer has a dopant ion concentration less than a dopant ion concentration of the first channel region and less than a dopant ion concentration of the second channel region.
15. 15. The semiconductor memory device according to claim 14, wherein a conductivity type of the semiconductor layer is opposite to a conductivity type of the first channel region and opposite to a conductivity type of the second channel region; the semiconductor layer has a dopant ion concentration less than a dopant ion concentration of the first channel region and less than a dopant ion concentration of the second channel region.
16. 16. The semiconductor memory device according to any one of claims 11 to 15, wherein the word line fills a gap between adjacent ones of the insulating layers.

Description

Semiconductor memory device having a memory cell with a memory cell having a memory cell with a memory cell Technical Field The present application relates to the field of semiconductor technology, and in particular, to a semiconductor memory device. Background With the development of semiconductor technology, semiconductor memory devices are widely used in various electronic devices. The semiconductor memory device includes Word Lines (WL), bit Lines (BL), transistors, and capacitors. The gate of the transistor is connected to the word line, the drain of the transistor is connected to the bit line, and the source of the transistor is connected to the capacitor. The transistor is controlled to be turned on or off by a word line, and data is read and written in the capacitor by a bit line. However, charge accumulation is easily generated in the transistor of the semiconductor memory device, affecting the data retention time. Disclosure of Invention The embodiment of the application provides a semiconductor memory device, which is used for achieving the effect of improving the data retention time. In a first aspect, an embodiment of the present application provides a semiconductor memory device including: A substrate on which a stacked structure defined by an isolation structure is provided; a word line extending in a vertical direction and located at one side of the stacked structure; A semiconductor layer located at the other side of the stacked structure and opposite to the word line; wherein the semiconductor layer and the word line are in direct contact. In one possible embodiment, the semiconductor layer extends in the vertical direction and directly contacts a portion of the sidewall of the stacked structure. In one possible embodiment, the stacked structure includes channel layers and insulating layers alternately arranged; each channel layer comprises a discontinuous first channel region and a discontinuous second channel region, and the first channel region and the second channel region are oppositely arranged at two sides of the word line. In one possible embodiment, the first channel region and the second channel region are both in direct contact with the semiconductor layer. In one possible embodiment, the first channel region, the second channel region and the semiconductor layer are the same conductivity type; the semiconductor layer has a dopant ion concentration less than a dopant ion concentration of the first channel region and less than a dopant ion concentration of the second channel region. In one possible embodiment, the semiconductor layer has a conductivity type opposite to a conductivity type of the first channel region and opposite to a conductivity type of the second channel region; the semiconductor layer has a dopant ion concentration less than a dopant ion concentration of the first channel region and less than a dopant ion concentration of the second channel region. In one possible implementation, the word lines fill gaps between adjacent ones of the insulating layers. In one possible embodiment, the semiconductor layer fills a gap between adjacent insulating layers. In one possible embodiment, the semiconductor layer directly contacts the sidewalls and top surface of the insulating layer. The semiconductor memory device comprises a substrate, word lines and a semiconductor layer, wherein the substrate is provided with a stacked structure defined by an isolation structure, the word lines extend in the vertical direction and are located on one side of the stacked structure, the semiconductor layer is located on the other side of the stacked structure and opposite to the word lines, and the semiconductor layer is in direct contact with the word lines. The semiconductor layer is separately arranged and is independent of the stacked structure, and the doping characteristics, the doping concentration and the like of the semiconductor layer can be utilized to improve the retention time of the floating body, so that the performance of the semiconductor memory device is improved. In addition, the semiconductor layer can be formed into an integral structure, and the manufacturing process of the semiconductor memory device can be simplified. In a second aspect, an embodiment of the present application provides a semiconductor memory device including: A substrate, on which a stack structure defined by an isolation structure is provided, the stack structure including channel layers and insulating layers alternately arranged; a word line extending in a vertical direction and located at one side of the stacked structure; A semiconductor layer located at the other side of the stacked structure and opposite to the word line; The portion of the word line in direct contact with the insulating layer has a first thickness, and the portion of the word line in direct contact with the semiconductor layer has a second thickness, the second thickness being greater than the first thickness. In one possi