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CN-122028417-A - Storage device

CN122028417ACN 122028417 ACN122028417 ACN 122028417ACN-122028417-A

Abstract

The present invention provides a novel memory device. The memory device includes a plurality of first wirings extending in a first direction, a plurality of memory element groups each including a plurality of memory elements each including a first transistor and a capacitor, and an oxide layer extending along a side of the first wirings. The gate electrode of the first transistor is electrically connected to the first wiring. The oxide layer includes a region in contact with the semiconductor layer of the first transistor. A second transistor is provided between adjacent memory element groups. A high power supply potential is supplied to one or both of the source electrode and the drain electrode of the second transistor.

Inventors

  • OHNUKI TATSUYA
  • KATO KIYOSHI
  • ATSUMI TOMOAKI
  • YAMAZAKI SHUNPEI

Assignees

  • 株式会社半导体能源研究所

Dates

Publication Date
20260512
Application Date
20190729
Priority Date
20180809

Claims (6)

  1. 1. A memory device comprising an array of cells, the array of cells comprising: A first sub-cell array having a first memory cell and a second memory cell, and A second array of subcells having a third memory cell, Wherein the first memory cell comprises a first transistor, the second memory cell comprises a second transistor, and the third memory cell comprises a third transistor, The second transistor is closest to the first transistor of the other transistors in the first sub-cell array, and the third transistor is closest to the second transistor of the other transistors in the second sub-cell array, The shortest distance between the gate electrode of the second transistor and the gate electrode of the third transistor is greater than the shortest distance between the gate electrode of the first transistor and the gate electrode of the second transistor, The first transistor, the second transistor and the third transistor are connected to the same word line, And the shortest distance between the gate electrode of the second transistor and the gate electrode of the third transistor is 3.5 M is less than or equal to m.
  2. 2. A memory device comprising an array of cells, the array of cells comprising: A first sub-cell array having a first memory cell and a second memory cell; A second sub-cell array having a third memory cell, and A dummy memory cell disposed between the second memory cell and the third memory cell, Wherein the first memory cell comprises a first transistor, the second memory cell comprises a second transistor, and the third memory cell comprises a third transistor, The second transistor is closest to the first transistor of the other transistors in the first sub-cell array, and the third transistor is closest to the second transistor of the other transistors in the second sub-cell array, The shortest distance between the gate electrode of the second transistor and the gate electrode of the third transistor is greater than the shortest distance between the gate electrode of the first transistor and the gate electrode of the second transistor, The first transistor, the second transistor and the third transistor are connected to the same word line, And the shortest distance between the gate electrode of the second transistor and the gate electrode of the third transistor is 3.5 M is less than or equal to m.
  3. 3. The storage device according to claim 1 or 2, Wherein each of the first transistor, the second transistor, and the third transistor includes a first oxide layer, a second oxide layer over the first oxide layer, source and drain electrodes over the second oxide layer, a third oxide layer between the source and drain electrodes, a first insulating layer over the third oxide layer, and a first conductive layer over the first insulating layer.
  4. 4. The memory device of claim 3, further comprising a second conductive layer under the first oxide layer.
  5. 5. The storage device according to claim 1 or 2, Wherein a holding potential of each of the first memory cell, the second memory cell, and the third memory cell is 0.6V or more.
  6. 6. The storage device according to claim 1 or 2, Wherein the shortest distance between the gate electrode of the first transistor and the gate electrode of the second transistor is 2.5 M is less than or equal to m.

Description

Storage device The invention is a divisional application of the invention patent application with international application number of PCT/IB2019/056433, international application date of 2019, 7 month and 29 days, application number of 201980051607.3 entering China national stage and named as 'storage device'. Technical Field One embodiment of the present invention relates to a memory device, a semiconductor device, or an electronic apparatus using these devices. Note that one embodiment of the present invention is not limited to the above-described technical field. One embodiment of the disclosed invention in this specification and the like relates to an object, a method, or a manufacturing method. In addition, one embodiment of the disclosed invention relates to a process, a machine, a product (process), or a composition (composition of matter). Note that in this specification and the like, a semiconductor device refers to all devices that can operate by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. Display devices (liquid crystal display devices, light-emitting display devices, and the like), projection devices, illumination devices, electro-optical devices, power storage devices, semiconductor circuits, imaging devices, electronic devices, and the like may include semiconductor devices. The display device, the projection device, the illumination device, the electro-optical device, the power storage device, the semiconductor circuit, the imaging device, the electronic apparatus, and the like can also be referred to as a semiconductor device. Background As a semiconductor thin film which can be used for a transistor, a silicon-based semiconductor material is widely known, and as other materials, an oxide semiconductor is attracting attention. As the oxide semiconductor, for example, a polyvalent metal oxide in addition to a unit metal oxide such as indium oxide, zinc oxide, or the like is known. Among the polyvalent metal oxides, particularly, in-Ga-Zn oxide (hereinafter also referred to as IGZO) has been studied particularly hot. As a result of studies on IGZO, it has been found that, in an oxide semiconductor, a CAAC (c-axis ALIGNED CRYSTALLINE: c-axis oriented crystallization) structure and a nc (nanocrystalline: nanocrystalline) structure are neither single crystal nor amorphous (see non-patent documents 1 to 3). Non-patent document 1 and non-patent document 2 disclose a technique for manufacturing a transistor using an oxide semiconductor having a CAAC structure. Non-patent document 4 and non-patent document 5 disclose that the oxide semiconductor having lower crystallinity than the CAAC structure and nc structure also has a minute crystal. An LSI and a display using IGZO for an active layer, which have extremely small off-state currents (see non-patent document 6) are known (see non-patent documents 7 and 8). Further, various semiconductor devices using a transistor including an oxide semiconductor in a channel formation region (hereinafter also referred to as an "OS transistor") have been proposed. Patent document 1 discloses an example in which an OS transistor is used for a memory cell (memory element) of a memory device. The OS transistor has very little current flowing between the source and the drain in the off-state (also referred to as "off-state current"), and thus the holding capacitor for the memory element can be reduced or eliminated. By reducing or eliminating the holding capacitor for the memory element, a memory device with high integration can be realized. [ Prior Art literature ] [ Patent literature ] [ Patent document 1] Japanese patent application laid-open No. 2012-256400 [ Non-patent literature ] [ Non-patent literature ] 1]S. Yamazaki et al., "SID Symposium Digest of Technical Papers", 2012, volume 43, issue 1, p.183-186 [ Non-patent literature ] 2]S. Yamazaki et al., "Japanese Journal of Applied Physics", 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 [ Non-patent document 3] S.Ito et al, "The Proceedings of AM-FPD'13 Digest of Technical Papers", 2013, p.151-154 [ Non-patent literature ] 4]S. Yamazaki et al., "ECS Journal of Solid State Science and Technology", 2014, volume 3, issue 9, p.Q3012-Q3022 [ Non-patent document 5] S, yamazaki, "ECS Transactions",2014, volume 64, issue 10, p.155-164 [ Non-patent document 6] K.Kato et al, "Japanese Journal of APPLIED PHYSICS", 2012, volume 51, p.021201-1-021201-7 [ Non-patent literature ] 7]S. Matsuda et al., "2015 Symposium on VLSI Technology Digest of Technical Papers", 2015, p.T216-T217 [ Non-patent document 8] S.Amano et al., "SID Symposium Digest of TECHNICAL PAPERS", 2010, volume 41, issue 1, p.626-629 Disclosure of Invention Technical problem to be solved by the invention It is an object of one embodiment of the present invention to provide a novel memory device or semiconductor device. Another object of one embodiment of the present invention i