CN-122028418-A - Semiconductor structure, forming method thereof and electronic equipment

CN122028418ACN 122028418 ACN122028418 ACN 122028418ACN-122028418-A

Abstract

The disclosure provides a semiconductor structure, a forming method thereof and electronic equipment, and relates to the technical field of semiconductors. The forming method comprises the steps of providing a substrate, forming a stacked structure on the substrate, wherein the stacked structure comprises a stacked semiconductor layer and an initial sacrificial layer, the stacked structure is provided with a groove, the groove penetrates through the stacked structure at least and exposes a part of the surface of the substrate, etching the initial sacrificial layer along a first direction to form a sacrificial layer, the sacrificial layer exposes a first part of the semiconductor layer, the end part of the first part of the semiconductor layer forms part of the side wall of the groove, the first direction is parallel to the substrate, a first dielectric layer is formed, covers the end face of the sacrificial layer and extends along the first direction to cover the part of the outer side wall of the first part of the semiconductor layer, and a first doping treatment is conducted on the exposed first part of the semiconductor layer by utilizing the first dielectric layer to form a doping region. The method can reduce leakage current of the device and improve the performance of the device.

Inventors

Guo Zean
ZHANG JUNCHAO
YUAN ZIHAO
LI HUIHUI
LIU MINGYUAN

Assignees

长鑫科技集团股份有限公司

Dates

Publication Date: 20260512
Application Date: 20260410

Claims (12)

1. A method of forming a semiconductor structure, comprising: Providing a substrate; Forming a stacked structure including a stacked semiconductor layer and an initial sacrificial layer on the substrate, the stacked structure having a trench penetrating at least the stacked structure and exposing a part of a surface of the substrate; Etching the initial sacrificial layer along a first direction to form a sacrificial layer, wherein the sacrificial layer exposes a first part of the semiconductor layer, and the end part of the first part of the semiconductor layer forms part of the side wall of the groove; Forming a first dielectric layer which covers the end face of the sacrificial layer and extends along the first direction to cover part of the outer side wall of the first part of the semiconductor layer; And carrying out first doping treatment on the exposed first part of the semiconductor layer by utilizing the first dielectric layer so as to form a doped region.
2. The method of forming a semiconductor structure of claim 1, wherein forming a first dielectric layer comprises: forming an initial first dielectric layer which covers the end face of the sacrificial layer, the outer side wall and the end face of the first part of the semiconductor layer at the same time and extends to cover the surface of the stacked structure; And removing part of the initial first dielectric layer positioned on the surface of the stacked structure, the end face of the first part of the semiconductor layer and the outer side wall of the first part of the semiconductor layer to form the first dielectric layer.
3. The method of forming a semiconductor structure of claim 2, comprising, after forming the initial first dielectric layer: and forming a second dielectric layer, wherein the second dielectric layer is at least filled in a gap between the first parts of the two adjacent semiconductor layers.
4. The method of claim 3, wherein removing a portion of the initial first dielectric layer located on a surface of the stacked structure, an end face of the first portion of the semiconductor layer, and an outer sidewall of the first portion of the semiconductor layer, comprises: and etching the initial first dielectric layer along the first direction by taking the second dielectric layer as a mask.
5. The method of claim 3 or 4, wherein the second dielectric layer has an etch rate that is less than an etch rate of the first dielectric layer.
6. The method of forming a semiconductor structure of claim 4, wherein after forming the doped region, comprising: and carrying out second doping treatment on the doped region so that a first source drain region is formed in a part of the doped region close to the groove, and a channel region is formed in the rest of the doped region, wherein doping ions of the second doping treatment are different from the doping ions of the first doping treatment.
7. The method of claim 6, wherein after forming the doped region, a portion of the semiconductor layer covered by the first dielectric layer is an undoped region, the method further comprising: And carrying out second doping treatment on the undoped region so as to enable at least part of the undoped region to form a second source drain region.
8. A semiconductor structure, comprising: A substrate; A stacked structure including a semiconductor layer and a sacrificial layer sequentially stacked on the substrate, the sacrificial layer exposing a first portion of the semiconductor layer; A trench penetrating at least the stacked structure and exposing a part of the surface of the substrate, wherein an end surface of the first portion of the semiconductor layer forms a part of a sidewall of the trench; The first part of the semiconductor layer at least comprises a first source drain region, a channel region and a second source drain region which are sequentially distributed along a first direction and a direction away from the groove, wherein the first direction is parallel to the substrate; And the first dielectric layer covers the second source drain region and is adjacent to the sacrificial layer, and the orthographic projection of the end surface of the first dielectric layer, which is close to the groove, on the substrate coincides with the orthographic projection of the boundary between the second source drain region and the channel region on the substrate.
9. The semiconductor structure of claim 8, wherein in the first direction, there is a first source-drain extension between the first source-drain region and the channel region, and a second source-drain extension between the second source-drain region and the channel region; the ion doping concentration of the second source-drain extension region is smaller than that of the first source-drain extension region.
10. The semiconductor structure of claim 8 or 9, wherein the second source drain region is an undoped region.
11. The semiconductor structure of claim 8 or 9, wherein the first source drain region and the second source drain region comprise different dopant ions.
12. An electronic device, comprising: a processing device, and a memory device electrically connected to the processing device, the memory device comprising the semiconductor structure of any of claims 8-11.

Description

Semiconductor structure, forming method thereof and electronic equipment Technical Field The disclosure relates to the technical field of semiconductors, and in particular relates to a semiconductor structure, a forming method thereof and electronic equipment. Background In order to meet the high integration requirement of the device, extend moore's law and maintain the performance of the device, the chip is changed from a planar transistor to a fin field effect transistor, but in the process of preparing the transistor, the transistor still has larger leakage current due to the limitation of the process steps such as diffusion, ion implantation and the like, and the performance of the transistor is influenced. It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art. Disclosure of Invention In view of the above, a semiconductor structure, a forming method thereof and an electronic device are provided, and the method can improve the leakage current of the device and improve the performance of the device. Other features and advantages of the present disclosure will be apparent from the following detailed description, or may be learned in part by the practice of the disclosure. According to one aspect of the present disclosure, there is provided a method of forming a semiconductor structure, the method comprising: Providing a substrate; Forming a stacked structure including a stacked semiconductor layer and an initial sacrificial layer on the substrate, the stacked structure having a trench penetrating at least the stacked structure and exposing a part of a surface of the substrate; Etching the initial sacrificial layer along a first direction to form a sacrificial layer, wherein the sacrificial layer exposes a first part of the semiconductor layer, and the end part of the first part of the semiconductor layer forms part of the side wall of the groove; Forming a first dielectric layer which covers the end face of the sacrificial layer and extends along the first direction to cover part of the outer side wall of the first part of the semiconductor layer; And carrying out first doping treatment on the exposed first part of the semiconductor layer by utilizing the first dielectric layer so as to form a doped region. In one exemplary embodiment of the present disclosure, forming a first dielectric layer includes: forming an initial first dielectric layer which covers the end face of the sacrificial layer, the outer side wall and the end face of the first part of the semiconductor layer at the same time and extends to cover the surface of the stacked structure; And removing part of the initial first dielectric layer positioned on the surface of the stacked structure, the end face of the first part of the semiconductor layer and the outer side wall of the first part of the semiconductor layer to form the first dielectric layer. In one exemplary embodiment of the present disclosure, after forming the initial first dielectric layer, it includes: and forming a second dielectric layer, wherein the second dielectric layer is at least filled in a gap between the first parts of the two adjacent semiconductor layers. In one exemplary embodiment of the present disclosure, removing a portion of the initial first dielectric layer located on a surface of the stacked structure, an end face of the first portion of the semiconductor layer, and an outer sidewall of the first portion of the semiconductor layer includes: and etching the initial first dielectric layer along the first direction by taking the second dielectric layer as a mask. In an exemplary embodiment of the present disclosure, the second dielectric layer has an etch rate that is less than an etch rate of the first dielectric layer. In one exemplary embodiment of the present disclosure, after forming the doped region, it includes: and carrying out second doping treatment on the doped region so that a first source drain region is formed in a part of the doped region close to the groove, and a channel region is formed in the rest of the doped region, wherein doping ions of the second doping treatment are different from the doping ions of the first doping treatment. In an exemplary embodiment of the present disclosure, after forming the doped region, a portion of the semiconductor layer covered by the first dielectric layer is an undoped region, and the method further includes: And carrying out second doping treatment on the undoped region so as to enable at least part of the undoped region to form a second source drain region. According to another aspect of the present disclosure, there is provided a semiconductor structure comprising: A substrate; A stacked structure including a semiconductor layer and a sacrificial layer sequentially stacked on the subst