CN-122028419-A - Semiconductor device and method for manufacturing the same

Abstract

The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate including a first region and a second region, a gate structure positioned over the substrate and extending from the first region to the second region, a laminate positioned in the second region over the substrate, a first support extending through the gate structure in the first region and arranged successively in a first direction, and a second support extending between the gate structure and the laminate in the second region in a second direction intersecting the first direction, at least one of the first supports may include a first protrusion protruding toward the second region, and the second support may include a second protrusion protruding toward the first region.

Inventors

• JIN ZAIHAO

Assignees

• 爱思开海力士有限公司

Dates

Publication Date

20260512

Application Date

20250508

Priority Date

20241104

Claims (20)

1. 1.A semiconductor device, the semiconductor device comprising: A substrate including a first region and a second region; A gate structure positioned over the substrate and extending from the first region to the second region; a laminate positioned in the second region over the substrate; a first support extending through the gate structure in the first region and arranged successively in a first direction, and A second support extending between the gate structure and the stack in a second direction intersecting the first direction in the second region, Wherein at least one of the first supports comprises a first protrusion protruding toward the second region, and Wherein the second support comprises a second protrusion protruding towards the first region.
2. 2. The semiconductor device of claim 1, wherein the at least one of the first supports comprises: a first body portion extending through the gate structure, and The first protrusion protrudes from the first body portion within the gate structure.
3. 3. The semiconductor device according to claim 1, wherein the second support includes: a second body portion extending between the gate structure and the stack, and And a second protrusion protruding from the second body portion within the gate structure.
4. 4. The semiconductor device according to claim 1, further comprising: A third support extending through the gate structure in the first region and extending in the first direction, and Fourth supports extending through the gate structure in the second region and arranged successively in the first direction.
5. 5. The semiconductor device according to claim 4, Wherein at least one of the third supports includes a third body portion extending through the gate structure and a third protrusion within the gate structure protruding from the third body portion toward the second region, and Wherein at least one of the fourth supports includes a fourth body portion extending through the gate structure and a fourth protrusion within the gate structure protruding from the fourth body portion toward the first region.
6. 6. The semiconductor device of claim 1, wherein the gate structure comprises: A first portion having a first height, and A second portion positioned on the first portion and having a second height that is less than the first height.
7. 7. The semiconductor device according to claim 6, further comprising: channel structures each comprising a first sub-channel structure extending through the first portion and a second sub-channel structure extending through the second portion and connected to the first sub-channel structure.
8. 8. The semiconductor device of claim 7, wherein at least one of the first protrusion or the second protrusion is positioned at a level corresponding to the first sub-channel structure.
9. 9. The semiconductor device according to claim 1, Wherein the gate structure comprises alternately stacked insulating layers and conductive layers, an Wherein the semiconductor device further comprises contact vias extending through the gate structure to connect to the conductive layers, respectively, and each contact via is positioned within the first region or the second region.
10. 10. The semiconductor device according to claim 1, further comprising: A peripheral circuit positioned above the substrate, and A contact plug extending through the laminate to electrically connect to the peripheral circuit and positioned in the second region.
11. 11. A semiconductor device, the semiconductor device comprising: a gate structure comprising a first portion and a second portion positioned on the first portion; a stack positioned at a level corresponding to the gate structure; A first support extending through the gate structure and arranged one after the other in a first direction, and A second support extending between the gate structure and the stack in a second direction intersecting the first direction, Wherein at least one of the first supports includes a first protrusion protruding toward the second support, the second support includes a second protrusion protruding toward the first support, and Wherein at least one of the first protrusion or the second protrusion is positioned at a level corresponding to the first portion.
12. 12. The semiconductor device according to claim 11, further comprising: a substrate including a first region and a second region, Wherein the gate structure is positioned above the substrate and extends from the first region to the second region, and Wherein the laminate is positioned above the substrate within the second region.
13. 13. The semiconductor device according to claim 12, Wherein the first protrusion protrudes toward the second region, and Wherein the second protrusion protrudes toward the first region.
14. 14. The semiconductor device according to claim 12, Wherein the gate structure comprises alternately stacked insulating layers and conductive layers, an Wherein the semiconductor device further comprises contact vias extending through the gate structure to connect to the conductive layers, respectively, and each contact via is positioned within the first region or the second region.
15. 15. The semiconductor device according to claim 12, further comprising: A peripheral circuit positioned above the substrate, and A contact plug extending through the laminate to electrically connect to the peripheral circuit and positioned in the second region.
16. 16. The semiconductor device of claim 11, wherein the at least one of the first supports comprises: a first body portion extending through the gate structure, and The first protrusion protrudes from the first body portion within the gate structure.
17. 17. The semiconductor device according to claim 11, wherein the second support includes: a second body portion extending between the gate structure and the stack, and The second protrusion protrudes from the second body portion within the gate structure.
18. 18. The semiconductor device according to claim 12, further comprising: A third support extending through the gate structure in the first region and extending in the first direction, and Fourth supports extending through the gate structure in the second region and arranged successively in the first direction.
19. 19. The semiconductor device according to claim 18, Wherein at least one of the third supports comprises a third body portion extending through the gate structure and a third protrusion within the gate structure protruding from the third body portion toward the fourth support, and Wherein at least one of the fourth supports includes a fourth body portion extending through the gate structure and a fourth protrusion within the gate structure protruding from the fourth body portion toward the third support.
20. 20. The semiconductor device according to claim 11, Wherein the first portion has a first height, and Wherein the second portion has a second height that is less than the first height.

Description

Semiconductor device and method for manufacturing the same Technical Field The present disclosure relates to electronic devices and methods of manufacturing electronic devices, and more particularly, to semiconductor devices and methods of manufacturing semiconductor devices. Background The degree of integration of a semiconductor device is mainly determined by the area occupied by the unit memory cells. Recently, as the improvement in the degree of integration of a semiconductor device in which memory cells are formed as a single layer on a substrate reaches a limit, a three-dimensional semiconductor device in which memory cells are stacked on a substrate is being proposed. In addition, various structures and manufacturing methods are being developed in order to improve the operational reliability of semiconductor devices. Disclosure of Invention According to an embodiment of the present disclosure, a semiconductor device may include a substrate including a first region and a second region, a gate structure positioned over the substrate and extending from the first region to the second region, a laminate positioned over the substrate in the second region, a first support extending through the gate structure in the first region and arranged successively in a first direction, and a second support extending between the gate structure and the laminate in a second direction intersecting the first direction in the second region, at least one of the first supports may include a first protrusion protruding toward the second region, and the second support may include a second protrusion protruding toward the first region. According to an embodiment of the present disclosure, a semiconductor device may include a gate structure including a first portion and a second portion positioned on the first portion, a stack positioned at a level corresponding to the gate structure, a first support extending through the gate structure and arranged successively in a first direction, and a second support extending between the gate structure and the stack along a second direction intersecting the first direction, at least one of the first supports may include a first protrusion protruding toward the second support, the second support may include a second protrusion protruding toward the first support, and at least one of the first protrusion or the second protrusion may be positioned at a level corresponding to the first portion. According to an embodiment of the present disclosure, a method of manufacturing a semiconductor device may include forming a first sub-stack, forming a first support hole extending through the first sub-stack, forming a support sacrificial layer in the first support hole, forming a second sub-stack on the first sub-stack, forming a second support hole extending through the second sub-stack and the first sub-stack and exposing a sidewall of the support sacrificial layer, removing the support sacrificial layer through the second support hole, and forming a support in the first support hole and the second support hole. According to an embodiment of the present disclosure, a method of manufacturing a semiconductor device may include forming a first sub-stack, forming a first channel hole extending through the first sub-stack, forming a first support hole extending through the first sub-stack, forming a channel sacrificial layer in the first channel hole, forming a support sacrificial layer in the first support hole, forming a second sub-stack on the first sub-stack, forming a second support hole extending through the second sub-stack and the first sub-stack and exposing a sidewall of the support sacrificial layer, removing the support sacrificial layer through the second support hole, and forming a support including a protrusion in the first support hole and the second support hole. Drawings Fig. 1A, 1B, 1C, and 1D are diagrams illustrating a semiconductor device according to an embodiment of the present disclosure. Fig. 2A, 2B, 2C, and 2D are diagrams illustrating a semiconductor device according to an embodiment of the present disclosure. Fig. 3A, 3B, 3C, 3D, and 3E are diagrams illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 4A, 4B, 4C, and 4D, fig. 5A, 5B, 5C, and 5D, fig. 6A, 6B, 6C, and 6D, fig. 7A, 7B, 7C, and 7D, and fig. 8A, 8B, 8C, and 8D are diagrams illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Detailed Description Embodiments of the present disclosure provide a semiconductor device having a stable structure and improved characteristics and a method of manufacturing the semiconductor device. According to the embodiments of the present technology, a semiconductor device having a stable structure and improved reliability can be provided. Hereinafter, embodiments according to the technical spirit of the present disclosure are described with reference to the ac