CN-122028420-A - Flash memory and manufacturing method thereof

Abstract

The invention provides a flash memory and a manufacturing method thereof. The flash memory includes a substrate, a first gate assembly, a first doped region, a first spacer, a cap layer, a hard mask layer, a first contact, a first protection layer, a second gate assembly, a second doped region, and a second spacer. The first protection layer is arranged between the first contact element and the hard mask layer, the top cover layer and the first spacer. The second protection layer is arranged between the first protection layer and the first contact element, the top cover layer, the first spacer and the substrate. The second gate assembly is disposed on the substrate in the peripheral region. The second doped region is arranged in the substrate at two sides of the second grid component. The second spacer is disposed on a sidewall of the second gate assembly.

Inventors

• XU BOYAN
• CHEN SIHAN
• ZHUANG ZHISHENG

Assignees

• 华邦电子股份有限公司

Dates

Publication Date

20260512

Application Date

20241218

Priority Date

20241112

Claims (19)

1. 1. A flash memory, comprising: A substrate having a memory region and a peripheral region; A first gate assembly disposed on the substrate in the memory region; The first doping areas are arranged in the substrate at two sides of the first grid component; A first spacer disposed on a sidewall of the first gate assembly; a capping layer disposed on a top surface of the first gate assembly; a hard mask layer disposed on the cap layer; a first contact disposed on the first doped region; a first protective layer disposed between the first contact and the hard mask layer, the cap layer, and the first spacer; A second protective layer disposed between the first protective layer and the first contact, the cap layer, the first spacer, and the substrate; a second gate assembly disposed on the substrate in the peripheral region; a second doped region disposed in the substrate at both sides of the second gate assembly, and And the second spacer is arranged on the side wall of the second grid component.
2. 2. The flash memory of claim 1, wherein a material of the first spacer is different from a material of the second spacer.
3. 3. The flash memory of claim 1, wherein a material of the first protective layer is different from a material of the second protective layer.
4. 4. The flash memory of claim 1, wherein a material of the second protective layer is different from a material of the cap layer and different from a material of the first spacer.
5. 5. The flash memory of claim 1, wherein a top surface of the first protective layer, a top surface of the second protective layer, and a top surface of the hard mask layer are coplanar.
6. 6. The flash memory of claim 1, wherein a material of the second protective layer is the same as a material of the hard mask layer.
7. 7. The flash memory of claim 1, wherein the hard mask layer comprises a first sub-hard mask layer and a second sub-hard mask layer, and the second sub-hard mask layer is disposed in the first sub-hard mask layer.
8. 8. The flash memory of claim 7, wherein the top surface of the first protective layer, the top surface of the second protective layer, the top surface of the first sub-hard mask layer, and the top surface of the second sub-hard mask layer are coplanar.
9. 9. The flash memory of claim 7, wherein the material of the first sub-hard mask layer is different from the material of the second sub-hard mask layer, and the material of the first sub-hard mask layer is the same as the material of the second protective layer.
10. 10. A method of manufacturing a flash memory, comprising: providing a substrate, wherein the substrate is provided with a memory area and a peripheral area; Sequentially forming a first gate assembly, a top cap layer and a hard mask layer on the substrate in the memory region; Forming a first spacer on a sidewall of the first gate assembly; forming a first doped region in the substrate at two sides of the first gate component; Forming a second gate assembly on the substrate in the peripheral region; forming a first contact on the first doped region; Forming a first protective layer between the first contact and the hard mask layer, the capping layer, and the first spacer; Forming a second protective layer between the first protective layer and the first contact, the cap layer, the first spacer, and the substrate; forming a second spacer on the sidewall of the second gate assembly, and And forming a second doped region in the substrate at two sides of the second gate component.
11. 11. The method of manufacturing a flash memory of claim 10, wherein the method of forming the first contact comprises: Forming a contact sacrificial pattern on the first doped region, and After the second protective layer is formed, the contact sacrificial pattern is replaced with a conductive material.
12. 12. The method of manufacturing a flash memory according to claim 10, wherein a material of the first spacer is different from a material of the second spacer.
13. 13. The method of manufacturing a flash memory according to claim 10, wherein a material of the first protective layer is different from a material of the second protective layer.
14. 14. The method of manufacturing a flash memory device according to claim 10, wherein a material of the second protective layer is different from a material of the cap layer and different from a material of the first spacer.
15. 15. The method of manufacturing a flash memory according to claim 10, wherein a material of the second protective layer is the same as a material of the hard mask layer.
16. 16. The method of manufacturing a flash memory according to claim 11, wherein the method of forming the contact sacrificial pattern, the first protective layer, the second protective layer, and the hard mask layer comprises: Forming a sacrificial material layer on the substrate after forming the cap layer, the first spacers, the first doped regions, and the second gate assembly; patterning the sacrificial material layer in the memory region to form the contact sacrificial pattern; Conformally forming a first dielectric material on the substrate; Forming a second dielectric material over the first dielectric material; Removing the first dielectric material and the second dielectric material on the top surface of the sacrificial material layer; Removing the second dielectric material on the cap layer to form a recess, and And forming the hard mask layer in the groove.
17. 17. The method of manufacturing a flash memory device according to claim 16, wherein the second spacer and the second doped region are formed after the forming of the hard mask layer, and further comprising forming a mask layer to cover the memory region after the forming of the hard mask layer and before the forming of the second spacer and the second doped region.
18. 18. The method of claim 17, further comprising forming a dielectric layer in the peripheral region after forming the second spacer and the second doped region and before removing the contact sacrificial pattern, wherein the dielectric layer covers the second gate element and the second doped region.
19. 19. The method of manufacturing a flash memory according to claim 18, wherein the method of replacing the contact sacrificial pattern with the conductive material comprises: removing the contact sacrificial pattern to form a first contact opening; Forming a patterned mask layer on the substrate, wherein the patterned mask layer covers the memory region and exposes a portion of the dielectric layer in the peripheral region; performing an etching process with the patterned mask layer as an etching mask to form a second contact opening in the dielectric layer in the peripheral region; Removing the patterned mask layer, and The conductive material is filled into the first contact opening and the second contact opening.

Description

Flash memory and manufacturing method thereof Technical Field The present invention relates to a flash memory and a method for manufacturing the same, and more particularly, to a flash memory having different structures and processes of spacers on sidewalls of gate devices in a memory region and spacers on sidewalls of gate devices in a peripheral region, and a method for manufacturing the same. Background In the current manufacturing process of flash memory, spacers of gate elements of a peripheral region are formed simultaneously with spacers of gate elements of a memory region. However, for the gate device in the memory region, the spacer is designed to reduce or prevent word line to bit line leakage, while for the gate device in the peripheral region, the spacer is designed to control device electrical properties, channel width, operation speed, etc., so that the two targets are different. With the shrinking of the process, the simultaneous fabrication of spacers for gate elements in the memory region and the periphery region poses several problems. For example, when the stack of spacers is added to prevent word line to bit line leakage, it is easy to increase the amount of electrical variation of the gate element with lightly doped drain (lightly doped drain, LDD) in the peripheral region and reduce the operation speed due to the complexity of etching the stack becomes high. Furthermore, after forming the spacers of the gate elements in the memory region and the peripheral region, doped regions are formed in the substrate on both sides of the gate elements in the memory region and the peripheral region in different steps. In addition, after forming the doped region, a heat treatment is typically performed to diffuse dopants in the doped region. In the current technology, a plurality of heat treatments are required, and when the heat treatment is performed on the doped region in the memory region, the formed doped region in the peripheral region is affected. Similarly, the heat treatment of the doped region in the peripheral region also affects the doped region already formed in the memory region. In this way, thermal budget is increased, and in particular, for high-performance or low-power flash memories, yield is easily reduced. Disclosure of Invention The invention is directed to a flash memory and a manufacturing method thereof, wherein a first protection layer and a second protection layer are arranged between a first contact element and a first grid electrode component in a memory area. The flash memory comprises a substrate, a first grid component, a first doped region, a first spacer, a top cover layer, a hard mask layer, a first contact, a first protective layer, a second grid component, a second doped region and a second spacer. The substrate has a memory region and a peripheral region. The first gate assembly is disposed on the substrate in the memory region. The first doped region is arranged in the substrate at two sides of the first grid component. The first spacer is disposed on a sidewall of the first gate assembly. The top cover layer is arranged on the top surface of the first grid component. The hard mask layer is disposed on the cap layer. The first contact is disposed on the first doped region. The first protection layer is arranged between the first contact element and the hard mask layer, the top cover layer and the first spacer. The second protection layer is arranged between the first protection layer and the first contact element, the top cover layer, the first spacer and the substrate. The second gate assembly is disposed on the substrate in the peripheral region. The second doped region is arranged in the substrate at two sides of the second grid component. The second spacer is arranged on the side wall of the second grid component. The manufacturing method of the flash memory comprises the following steps. A substrate is provided, wherein the substrate has a memory region and a peripheral region. A first gate element, a cap layer and a hard mask layer are sequentially formed on a substrate in a memory region. A first spacer is formed on a sidewall of the first gate element. A first doped region is formed in the substrate on both sides of the first gate element. A second gate assembly is formed on the substrate in the peripheral region. A first contact is formed on the first doped region. A first protective layer is formed between the first contact and the hard mask layer, the cap layer, and the first spacer. A second protective layer is formed between the first protective layer and the first contact, the cap layer, the first spacer and the substrate. A second spacer is formed on a sidewall of the second gate assembly. And forming a second doped region in the substrate at two sides of the second gate component. Based on the above, in the flash memory of the present invention, the first protection layer and the second protection layer are disposed between the first contact and