CN-122028421-A - Manufacturing method of embedded flash memory

CN122028421ACN 122028421 ACN122028421 ACN 122028421ACN-122028421-A

Abstract

The invention provides a manufacturing method of an embedded flash memory. The method comprises the steps of providing a substrate, defining a source line area with a first space and a bit line area with a second space, wherein the first space is smaller than the second space, depositing conductive materials, enabling the conductive materials to be in a filled state in the source line area and to be in a non-filled state in the bit line area by utilizing space difference, conducting patterning on the conductive materials, forming an erasing gate in the source line area, and forming a word line in a self-aligned mode in the bit line area. The invention utilizes the difference of physical filling characteristics and is matched with planarization and etching back processes, thereby realizing the self-alignment formation of word lines, needing no extra photomask, effectively reducing the height of a storage unit, avoiding alignment errors and improving the yield of devices.

Inventors

JIANG HUI
ZHOU YANG

Assignees

华虹半导体(无锡)有限公司

Dates

Publication Date: 20260512
Application Date: 20260112

Claims (12)

1. A method for manufacturing an embedded flash memory, comprising: providing a substrate, defining a source line region and a bit line region on the substrate, wherein the source line region has a first interval, the bit line region has a second interval, and the first interval is smaller than the second interval; Depositing conductive materials in the source line area and the bit line area, and enabling the conductive materials to be in a filled state in the source line area and to be in a non-filled state in the bit line area by utilizing the difference between the first space and the second space; and thirdly, carrying out patterning treatment on the conductive material, forming an erasing gate in the source line region, and forming a word line in the bit line region in a self-aligned manner.
2. The method of manufacturing an embedded flash memory device according to claim 1, wherein in the first step, a pair of gate stack structures is formed on the substrate, the gate stack structures include a gate dielectric layer, a floating gate and control gate isolation dielectric layer, and a control gate from bottom to top, the source line region is located between the pair of gate stack structures, and the bit line region is located outside the gate stack structures.
3. The method of claim 1, wherein in the first step, the source line region and the bit line region are defined by a masking process, and etching, wet cleaning, and furnace process steps are performed.
4. The method of manufacturing an embedded flash memory as claimed in claim 1, further comprising performing source line ion implantation and annealing in the source line region after the first step and before the second step.
5. The method of manufacturing an embedded flash memory device of claim 4, further comprising growing a tunneling dielectric layer and annealing the tunneling dielectric layer in the source line region and the bit line region after the source line ion implantation and annealing.
6. The method of manufacturing an embedded flash memory as claimed in claim 5, wherein the tunneling dielectric layer is made of silicon oxide.
7. The method of manufacturing an embedded flash memory according to claim 1, wherein in the second step, the conductive material is polysilicon.
8. The method of manufacturing an embedded flash memory as claimed in claim 1, further comprising performing a rapid thermal oxidation process on the deposited conductive material after the second step and before the third step.
9. The method of manufacturing an embedded flash memory device according to claim 1, wherein in the third step, the patterning process includes a chemical mechanical polishing process and a global etching back process, and the word line is formed by self-aligned etching while reducing a height of the memory cell through the chemical mechanical polishing process and the global etching back process.
10. The method of manufacturing an embedded flash memory as claimed in claim 1, further comprising growing a sidewall on the sidewall of the word line after the third step, and performing ion implantation.
11. The method of manufacturing an embedded flash memory device of claim 10, further comprising forming a metal silicide layer on exposed surfaces of the erase gate, the word line and the substrate after the ion implantation.
12. The method of manufacturing an embedded flash memory as set forth in claim 1, further comprising depositing an interlayer dielectric layer, opening a contact hole in the interlayer dielectric layer, and filling a conductive plug in the contact hole to draw out the metal silicide layer after forming the metal silicide layer.

Description

Manufacturing method of embedded flash memory Technical Field The invention relates to the technical field of semiconductors, in particular to a manufacturing method of an embedded flash memory. Background Nonvolatile embedded flash memory (eFflash) has the advantages of high integration level, low power consumption, high reliability and the like, and is widely applied to a plurality of fields such as Microprocessors (MCU), automobile electronics, smart cards and the like. In a conventional embedded flash memory manufacturing process, flash memory cells are typically formed of structures such as a substrate, an independent Erase Gate (EG), a Control Gate (CG), a Floating Gate (FG), a Word Line (WL), a Bit Line (BL), and a Source Line (SL). The individual gate structures are typically isolated by oxide layers, such as shallow trench isolation silicon oxide, coupling oxide, floating gate/control gate isolation dielectric, and tunneling oxide. The existing word line and erase gate formation processes are often complex, and often require multiple masks to define different regions, which not only increases the process cost, but also may lead to non-uniformity in device performance due to photolithographic alignment errors. Particularly, in the pursuit of higher integration, how to effectively form the word lines of the sidewall structures while ensuring the filling quality of the erase gates and reducing the height of the memory cells (cells) is a challenge of the current process. Therefore, there is a need for a flash memory fabrication process that can utilize features of the structure itself to achieve self-alignment, reduce mask costs, and optimize device topography. Disclosure of Invention The invention provides a manufacturing method of an embedded flash memory, which aims to solve the problems of complex word line and erasing gate forming process, high photomask cost and easy occurrence of photoetching alignment errors in the prior art. In order to solve the technical problems, the invention provides a manufacturing method of an embedded flash memory, which comprises the following steps: providing a substrate, defining a source line region and a bit line region on the substrate, wherein the source line region has a first interval, the bit line region has a second interval, and the first interval is smaller than the second interval; Depositing conductive materials in the source line area and the bit line area, and enabling the conductive materials to be in a filled state in the source line area and to be in a non-filled state in the bit line area by utilizing the difference between the first space and the second space; and thirdly, carrying out patterning treatment on the conductive material, forming an erasing gate in the source line region, and forming a word line in the bit line region in a self-aligned manner. Preferably, in the first step, a pair of gate stack structures are formed on the substrate, the gate stack structures comprise a gate dielectric layer, a floating gate and control gate isolation dielectric layer and a control gate from bottom to top, the source line region is located between the pair of gate stack structures, and the bit line region is located outside the gate stack structures. Preferably, in step one, the source line region and the bit line region are defined by a mask process, and etching, wet cleaning and furnace tube processes are performed. Preferably, after the first step and before the second step, the method further comprises the steps of carrying out source line ion implantation on the source line region and carrying out annealing treatment. Preferably, after the source line ion implantation and annealing treatment, a tunneling dielectric layer is grown in the source line region and the bit line region and annealing treatment is performed. Preferably, the tunneling dielectric layer is made of silicon oxide. Preferably, in the second step, the conductive material is polysilicon. Preferably, after the second step and before the third step, the method further comprises the step of performing rapid thermal oxidation treatment on the deposited conductive material. Preferably, in the third step, the patterning process comprises a chemical mechanical polishing process and a full back etching process, and the word line is formed by self-aligned etching while the height of the memory cell is reduced through the chemical mechanical polishing process and the full back etching process. Preferably, after the third step, the method further comprises the steps of growing side walls on the side walls of the formed word lines and performing ion implantation. Preferably, after the ion implantation, a metal silicide layer is formed on the exposed surfaces of the erase gate, the word line and the substrate. Preferably, after the metal silicide layer is formed, an interlayer dielectric layer is deposited, a contact hole is formed in the interlayer dielectric layer, and a conductive plug is f