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CN-122028422-A - Multiple programmable device structure and method of manufacturing the same

CN122028422ACN 122028422 ACN122028422 ACN 122028422ACN-122028422-A

Abstract

The application provides a multi-time programmable device structure and a manufacturing method thereof. The structure comprises a substrate, a shallow trench isolation structure, a floating gate and a contact structure. The bottom surface of the control gate contact is located above the shallow trench isolation structure, the control gate active region is removed below the control gate contact, the control gate contact is arranged adjacent to the side wall of the floating gate, the side surface of the control gate contact is used as a control gate, and capacitive coupling is formed between the control gate contact and the side wall of the floating gate through a dielectric material. According to the application, the lateral coupling is realized by removing the control gate active region and utilizing the contact piece, PN junctions between the control gate and the well region are eliminated, complete medium isolation is realized, the problems of insufficient withstand voltage and leakage risk of the traditional device are solved, the size of the device is effectively reduced, the programming efficiency is improved, and the CMOS technology is compatible.

Inventors

  • XU ZHAOZHAO
  • LIU DONGHUA

Assignees

  • 华虹半导体(无锡)有限公司
  • 上海华虹宏力半导体制造有限公司

Dates

Publication Date
20260512
Application Date
20260112

Claims (19)

  1. 1. A multiple-time programmable device structure, comprising: A semiconductor substrate (100); a shallow trench isolation structure (101) formed in the semiconductor substrate (100); a well region (102) formed in the semiconductor substrate (100); Source and drain regions (103,109) formed in the device active region within the well region (102); a floating gate structure (105) located above the semiconductor substrate (100) and isolated from the semiconductor substrate (100) by a gate dielectric layer (104); an interlayer dielectric layer covering the semiconductor substrate (100) and the floating gate structure (105), and A contact structure (110) passing through the interlayer dielectric layer; Wherein the contact structure (110) comprises a source-drain contact (110-1, 110-2) electrically connected to the source and drain regions (103,109), and a control gate contact (110-3) as a control gate; The bottom surface of the control gate contact (110-3) is located above the shallow trench isolation structure (101), and a control gate active region is removed below the control gate contact (110-3); The control gate contact (110-3) is arranged on the side edge of the floating gate structure (105), the side surface of the control gate contact (110-3) is used as a control gate, and a capacitive coupling structure is formed by a dielectric material and the side wall of the floating gate structure (105) so as to realize the control gate function.
  2. 2. The multi-time programmable device structure of claim 1, wherein the control gate contacts (110-3) are distributed on left and right sides of the floating gate structure (105) to increase a coupling area between the control gate contacts (110-3) and the floating gate structure (105).
  3. 3. The multi-time programmable device structure of claim 2, wherein the control gate contacts (110-3) distributed on both sides of the floating gate structure (105) are configured as an elongated contact hole structure or a multi-row point contact hole structure.
  4. 4. The multi-time programmable device structure of claim 1, wherein sidewalls of the floating gate structure (105) are formed with sidewall structures (107, 108), wherein the dielectric material comprising the capacitive coupling structure comprises the sidewall structures (107, 108) and a portion of the interlayer dielectric layer between the control gate contact (110-3) and the floating gate structure (105), and wherein the control gate contact (110-3) applies a coupling voltage to the floating gate structure (105) through the dielectric material.
  5. 5. The multi-time programmable device structure of claim 1, wherein said control gate contact (110-3) achieves complete dielectric layer isolation from said well region (102) and said source region as a source line, said dielectric layer isolation being provided at least by said shallow trench isolation structure (101).
  6. 6. The multiple programmable device structure of claim 1, wherein the multiple programmable device structure is compatible with a Complementary Metal Oxide Semiconductor (CMOS) process.
  7. 7. The multiple programmable device structure of claim 1, wherein said semiconductor substrate (100) comprises a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, and/or a compound semiconductor substrate.
  8. 8. The multi-time programmable device structure of claim 1, wherein the material of the floating gate structure (105) comprises doped polysilicon, undoped polysilicon, amorphous silicon, and/or polysilicon germanium.
  9. 9. The multi-time programmable device structure of claim 1, wherein the gate dielectric layer (104), the shallow trench isolation structure (101), and the interlayer dielectric layer are independently selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, fluorosilicate glass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), spin-on glass (SOG), tetraethoxysilane (TEOS) oxide, carbon doped silicon oxide, low k dielectric materials, and/or high k dielectric materials.
  10. 10. The multi-time programmable device structure of claim 1, wherein the conductive material of the control gate contact (110-3) comprises tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), cobalt (Co), nickel (Ni), a metal silicide, or alloys and combinations thereof.
  11. 11. A method of fabricating a multiple-time programmable device structure, comprising: Step one, forming a shallow trench isolation structure (101) and a well region (102) on a semiconductor substrate (100), wherein the shallow trench isolation structure (101) is used for removing an active region for forming a control gate while defining the active region of the device; Forming a gate dielectric layer (104) and a floating gate structure (105) on the semiconductor substrate (100), and performing an ion implantation process to form a source region and a drain region (103,109) in a device active region in the well region (102); And thirdly, depositing an interlayer dielectric layer, and forming a contact structure (110) in the interlayer dielectric layer through etching and filling conductive materials, wherein forming the contact structure (110) comprises forming a control gate contact (110-3) which is positioned above the shallow trench isolation structure (101) and serves as a control gate, the control gate contact (110-3) is distributed along the side wall of the floating gate structure (105), and a coupling effect is achieved between the side surface of the control gate contact (110-3) and the floating gate structure (105) by using the side surface of the control gate contact as the control gate.
  12. 12. The method of manufacturing a multi-time programmable device structure of claim 11, wherein the method of manufacturing is compatible with a Complementary Metal Oxide Semiconductor (CMOS) process.
  13. 13. The method of manufacturing a multi-time programmable device structure of claim 11, wherein in step three, forming said contact structure (110) further comprises forming source-drain contacts (110-1, 110-2) electrically connected to said source and drain regions (103,109).
  14. 14. The method of manufacturing a multi-time programmable device structure of claim 11, further comprising the step of forming sidewall structures (107, 108) on sidewalls of said floating gate structure (105) after forming said floating gate structure (105) in step two.
  15. 15. The method of manufacturing a multi-time programmable device structure according to claim 14, wherein in step three, a coupling medium is between the control gate contact (110-3) and the floating gate structure (105) through the sidewall structures (107, 108) and the interlayer dielectric layer.
  16. 16. The method of manufacturing a multi-time programmable device structure of claim 11, wherein in step three, the control gate contacts (110-3) are formed to be distributed on both left and right sides of the floating gate structure (105) to increase a coupling area between the control gate contacts (110-3) and the floating gate structure (105).
  17. 17. The method of manufacturing a multi-time programmable device structure according to claim 16, wherein in the third step, the control gate contacts (110-3) distributed on both sides of the floating gate structure (105) are configured in a shape of an elongated contact hole structure or a multi-row point contact hole structure.
  18. 18. The method of manufacturing a multi-time programmable device structure of claim 11, wherein in step three, a bottom surface of said control gate contact (110-3) directly contacts said shallow trench isolation structure (101) to thereby achieve dielectric layer isolation between the control gate and the source line.
  19. 19. The method of manufacturing a multi-time programmable device structure of claim 11, wherein in the second step, the ion implantation process comprises a lightly doped drain implantation process, and the lightly doped drain implantation process uses N-type impurities.

Description

Multiple programmable device structure and method of manufacturing the same Technical Field The present invention relates to the field of semiconductor technology, and in particular, to a multiple programmable device structure and a method for manufacturing the same. Background Multiple Time Programmable (MTP) memory is a non-volatile memory device that is highly compatible with Complementary Metal Oxide Semiconductor (CMOS) technology, and is widely used in power management, display driving, and micro-controller chips for storing critical configuration parameters or codes. These devices are mainly based on floating gate technology, which records data by controlling the storage state of charges in a floating gate. Fig. 1 and 2 show a schematic diagram of a typical prior art MTP device. Fig. 1 is a plan view of the layout of the device, and fig. 2 is a schematic diagram of a cross-sectional structure corresponding to Cut lines Cut1 and Cut2 in fig. 1. As shown in fig. 1, the layout of a conventional MTP device typically includes two separate active regions, a lower channel active region and an upper CG (control gate) active region. Floating gate polysilicon (FG) spans both active regions. Wherein Cut1 tangent passes through the channel region and Cut2 tangent passes through the control gate region. As shown in fig. 2, a detailed cross-sectional structure along Cut1 and Cut2 is provided. The structure is based on a semiconductor substrate 100 and is region isolated by Shallow Trench Isolation (STI) 101. In the channel region (left side) shown in Cut1, source and drain regions are formed in P-well 102. Specifically, the N-type Lightly Doped Drain (LDD) implantation region 103 and the N-type heavily doped implantation region 109 are included. The floating gate polysilicon layer 105 is located on the gate insulating dielectric layer 104, and a first sidewall dielectric layer 107 and a second sidewall dielectric layer 108 are formed on the sidewalls thereof. Bit Lines (BL) and Source Lines (SL) are respectively led out through BL contact holes 110-1 and SL contact holes 110-2 in the interlayer dielectric layer. In the control gate region shown at Cut2 (right side), the control gate CG is actually constituted by an N-type implanted region 206 (CG active region) formed in the substrate. The floating gate polysilicon layer 105 is coupled to the CG active region 206 through a control gate insulating dielectric layer 204. The control gate signal is introduced through control gate contact hole 110-3 that directly overlies CG active region 206. It is often necessary to establish specific voltage conditions between the control gate CG, P-well 102, source line SL and bit line BL when the device is subjected to a programming operation. For example, control gate CG is connected to 9V, P-well 102 is grounded (0V), source line SL is grounded (0V), and bit line BL is connected to 5V. At this time, a high voltage difference of about 9V exists between the CG active region 206 (9V), the P-well 102 (0V) and the source terminal 103 (0V). However, as can be seen in fig. 2, the CG active region 206 is isolated from the P-well 102 and the source region of the channel region mainly by means of STI 101 and PN junction. Because a junction isolation mechanism is adopted between the CG and the P-shaped well, and the limitation of reverse breakdown voltage exists, the voltage applied to the CG cannot be too large, and the voltage becomes a bottleneck for restricting the improvement of programming efficiency. If the CG voltage is increased in order to improve the programming efficiency, the doping profile between CG active region 206, P-well 102 and source region 103 must be optimized, while the dimension (width) of STI 101 between the CG active region and the source region must be significantly increased to prevent breakdown or leakage. This increase in STI size will directly result in a further increase in overall device size, which is detrimental to high density integration. Therefore, a new MTP device structure is needed in the industry, which can effectively improve the isolation withstand voltage between the control gate and the source line/well region without increasing or even reducing the device size, thereby improving the programming efficiency and reducing the leakage risk. Disclosure of Invention The application provides a multi-time programmable device structure and a manufacturing method thereof, which are used for solving the problems of insufficient voltage withstand capability and high leakage risk caused by PN junction isolation between a control gate and a well region or a source line of the multi-time programmable device in the prior art, and the problem of reduced device integration caused by the fact that the isolation size must be increased to prevent high-voltage breakdown. The application provides a multiple programmable device structure, comprising: a semiconductor substrate; A shallow trench isolation structure for