CN-122028423-A - Method for manufacturing semiconductor device

Abstract

The invention provides a manufacturing method of a semiconductor device, which comprises the steps of providing a semiconductor substrate, forming a groove structure on the substrate, depositing a polycrystalline silicon seed layer on the inner surface of the groove by adopting a chemical vapor deposition process, depositing a main polycrystalline silicon layer on the seed layer until the groove is filled by adopting the chemical vapor deposition process, wherein the process pressure of the second step is set to be higher than that of the third step so as to promote the diffusion of reaction gas into the bottom of the groove. According to the invention, the probability of gas entering the high depth-to-width ratio groove is increased through high-pressure pre-reaction, uniform nucleation points are provided on the side wall and the bottom to form fine grains, filling uniformity is improved, diffusion limitation is overcome, bottom cavity problem during filling of polysilicon of the small-size ETOX device is effectively solved, and device yield is improved.

Inventors

• LU DECHENG
• ZHAO XUDONG
• YANG DEMING
• DU MINGFENG
• LIU BOTONG

Assignees

• 华虹半导体制造(无锡)有限公司
• 华虹半导体(无锡)有限公司

Dates

Publication Date

20260512

Application Date

20260128

Claims (13)

1. 1. A method of manufacturing a semiconductor device, comprising at least: step one, providing a semiconductor substrate, wherein a groove structure is formed on the semiconductor substrate; depositing a polysilicon seed crystal layer on the inner surface of the groove structure by adopting a chemical vapor deposition process; depositing a main polysilicon layer on the polysilicon seed crystal layer by adopting a chemical vapor deposition process until the trench structure is filled; The process pressure in the second step is set to be higher than the process pressure in the third step so as to promote the diffusion of the reaction gas into the bottom of the groove structure.
2. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the first step, the trench structure is a gate trench, an isolation trench or a via structure for forming a gate of a flash memory device.
3. 3. The method of manufacturing a semiconductor device according to claim 1, wherein in the first step, the aspect ratio of the trench structure is greater than 10:1.
4. 4. The method of manufacturing a semiconductor device according to claim 1, wherein before the second step, the method further comprises the step of forming a tunneling dielectric layer on the semiconductor substrate.
5. 5. The method of manufacturing a semiconductor device according to claim 1, wherein in the second and third steps, the chemical vapor deposition process is specifically a low pressure chemical vapor deposition process.
6. 6. The method of manufacturing a semiconductor device according to claim 1, wherein in the second step, the reactive source gas used for depositing the polysilicon seed layer includes a silicon source gas.
7. 7. The method of manufacturing a semiconductor device according to claim 6, wherein in the second step, the silicon source gas is silane.
8. 8. The method of manufacturing a semiconductor device according to claim 1, wherein in the second step, a process temperature for depositing the polysilicon seed layer is 600 ℃ to 620 ℃.
9. 9. The method of manufacturing a semiconductor device according to claim 1, wherein in the second step, the process time for depositing the polysilicon seed layer is 20s to 50s.
10. 10. The method of manufacturing a semiconductor device according to claim 1, wherein in the second step, a flow rate of the gas for depositing the polysilicon seed layer is 200sccm to 400sccm.
11. 11. The method of manufacturing a semiconductor device according to claim 1, wherein in the second step, the process pressure for depositing the polysilicon seed layer is 0.15Torr to 0.35Torr.
12. 12. The method of manufacturing a semiconductor device according to claim 1, wherein in the second step, the rotation speed of the reaction boat is increased during the deposition of the polysilicon seed layer to improve uniformity of the gas flow distribution.
13. 13. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is an ETOX-structured flash memory, and the polysilicon seed layer and the main polysilicon layer are used to form a floating gate of the flash memory.

Description

Method for manufacturing semiconductor device Technical Field The present invention relates to the field of integrated circuit fabrication, and more particularly, to a method of fabricating a semiconductor device. Background With the continuous improvement of the integration level and the miniaturization of the feature size of semiconductor devices, flash memories are widely used in various electronic products. In order to obtain a faster storage speed, a longer storage time, and a larger storage capacity, the requirements for flash memory devices are also increasing. Among them, the ETOX (EPROM Tunnel Oxide EPROM) -structured flash memory is widely used because of its high reliability. Memory performance is one of the key parameters in evaluating flash memory. In the manufacturing process of chips, particularly in the formation process of gates, the process quality is inevitably affected by various factors such as deposition rate, gas flow field, diffusion rate, etc. Currently, in the process of manufacturing the gate electrode, a vertical furnace tube is generally used for performing a Low Pressure Chemical Vapor Deposition (LPCVD) process of polysilicon. As device feature sizes enter the nanoscale, the aspect ratios of gate trenches, isolation trenches, and via structures have increased significantly, having been raised above 10:1. Polysilicon filling in such high aspect ratio trenches presents a significant challenge. Specifically, the diffusion of the reactant (e.g., silane SiH 4) to the bottom of the trench is limited, resulting in an insufficient deposition rate at the bottom, and at the same time, reaction byproducts (e.g., hydrogen H2) are difficult to drain from the bottom of the deep trench. This imbalance in mass transport results in significantly lower deposition rates at the bottom of the trench than at the top, and is very prone to defects such as voids (Void) and cantilever structures within the trench. The existing polysilicon standard process often causes bottom cavity or side wall defects in the formed floating gate due to insufficient filling capability. Such defects easily cause phenomena such as rising of resistance (Rs), gate leakage and the like, seriously affect the electrical performance of the device, lead to higher failure rate, and finally shorten the service life of the device or lead to failure of the device. Therefore, how to overcome the diffusion limitation in the high aspect ratio structure, improve the filling uniformity of polysilicon, and eliminate the filling void is a core problem to be solved in the current flash memory manufacturing. Disclosure of Invention The invention aims to solve the technical problems that in the prior art, along with miniaturization of the feature size of a semiconductor device, particularly for small-size ETOX products, when polysilicon is filled in a high aspect ratio groove, diffusion is limited, byproducts are difficult to discharge, the bottom deposition rate is insufficient, a cavity and a cantilever structure are easy to generate, and further the impedance of the device is increased, electric leakage and yield are reduced. The invention provides a method for manufacturing a semiconductor device, which comprises the following steps: step one, providing a semiconductor substrate, wherein a groove structure is formed on the semiconductor substrate; depositing a polysilicon seed crystal layer on the inner surface of the groove structure by adopting a chemical vapor deposition process; And thirdly, depositing a main polysilicon layer on the polysilicon seed crystal layer by adopting a chemical vapor deposition process until the trench structure is filled, wherein the process pressure in the second step is set to be higher than the process pressure in the third step so as to promote the diffusion of reaction gas into the bottom of the trench structure. Preferably, in step one, the trench structure is a gate trench, an isolation trench or a via structure for forming a gate of a flash memory device. Preferably, in the first step, the aspect ratio of the trench structure is greater than 10:1. Preferably, before the second step, the method further comprises the step of forming a tunneling dielectric layer on the semiconductor substrate. Preferably, in the second step and the third step, the chemical vapor deposition process is specifically a low-pressure chemical vapor deposition process. Preferably, in the second step, the reactive source gas used for depositing the polysilicon seed layer includes a silicon source gas. Preferably, in the second step, the silicon source gas is silane. Preferably, in the second step, the process temperature for depositing the polysilicon seed layer is 600 ℃ to 620 ℃. Preferably, in the second step, the process time for depositing the polysilicon seed layer is 20 s-50 s. Preferably, in the second step, the gas flow rate for depositing the polysilicon seed layer is 200sccm to 400sccm. Preferably, in the second step