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CN-122028424-A - Method for improving flash memory reliability

CN122028424ACN 122028424 ACN122028424 ACN 122028424ACN-122028424-A

Abstract

The invention provides a method for improving the reliability of a flash memory. After a substrate with a memory cell structure is provided, a layer of protection material (such as silicon nitride) resistant to wet corrosion is deposited, and a protection side wall is formed only outside a first side wall of the memory cell side wall by etching. In the subsequent wet etching process, the protective side wall blocks the chemical agent from corroding the first side wall, so that the first side wall is prevented from shrinking inwards and forming a recess at the top end of the control gate. The integrity of the subsequently formed side wall structure is ensured, and the problem of short circuit between the control gate and the bit line contact hole caused by side wall fracture is avoided, so that the yield and the reliability of the flash memory are improved.

Inventors

  • DONG QIAN
  • DANG YANG
  • JIANG HONG

Assignees

  • 华虹半导体制造(无锡)有限公司
  • 华虹半导体(无锡)有限公司
  • 上海华虹宏力半导体制造有限公司

Dates

Publication Date
20260512
Application Date
20260128

Claims (13)

  1. 1. A method for improving the reliability of a flash memory, comprising: step one, providing a semiconductor substrate, wherein a storage unit structure is manufactured on the semiconductor substrate; Step two, depositing a protective material layer on the surface of the semiconductor substrate and the memory cell structure; etching the protective material layer, removing the protective material layer on the flat surface, and reserving the protective material layer on the side wall of the storage unit structure to form a protective side wall; Etching to remove the exposed control gate conducting layer and the floating gate conducting layer below the exposed control gate conducting layer, and performing a wet cleaning process, wherein the protection side wall is used for protecting the memory cell structure from being damaged by etching of the wet cleaning process; and fifthly, forming a subsequent side wall structure on the semiconductor substrate.
  2. 2. The method for improving the reliability of the flash memory according to claim 1, wherein: in the first step, the method for manufacturing the memory cell structure includes: Sequentially forming a dielectric layer, a floating gate conducting layer, an interelectrode dielectric layer, a control gate conducting layer and a hard mask layer on the semiconductor substrate; patterning the hard mask layer against etching to open an opening; Forming a first side wall on the side wall of the opening; Etching the exposed control gate conductive layer by taking the hard mask layer and the first side wall as masks; Forming a second side wall; etching the exposed floating gate conducting layer by taking the second side wall as a mask to define a floating gate structure; Forming a tunneling dielectric layer; Forming a word line conductive layer filling the opening; Forming a protective cap layer on the word line conductive layer; and removing the hard mask layer.
  3. 3. The method of claim 2, wherein in step one, the semiconductor substrate further defines a logic region, wherein after removing the hard mask layer, the method further comprises forming a logic region conductive layer on the logic region, wherein the logic region conductive layer and the memory cell structure serve as a base structure before performing the deposition process of step two.
  4. 4. The method of claim 2, wherein in step three, the protection sidewall is formed only on an outer sidewall of the first sidewall.
  5. 5. The method of claim 4, wherein in the fourth step, the protection sidewall formed on the outer sidewall of the first sidewall blocks the chemical agent in the wet cleaning process from contacting the first sidewall to prevent the first sidewall from shrinking.
  6. 6. The method for improving reliability of flash memory as recited in claim 5, wherein the first sidewall is recessed to expose and recess a top end of the control gate conductive layer.
  7. 7. The method of claim 5, wherein in step five, the subsequent sidewall structures are formed on sidewalls of the memory cell structure after removing portions of the floating gate conductive layer and the control gate conductive layer.
  8. 8. The method of claim 6, wherein in the fifth step, the first sidewall is prevented from shrinking, so that the subsequent sidewall structure is prevented from breaking at the top end of the control gate conductive layer after etching.
  9. 9. The method of claim 1, wherein in the second step, the protective material layer is selected from a dielectric material resistant to wet etching.
  10. 10. The method for improving reliability of flash memory of claim 9 wherein said dielectric material comprises silicon nitride.
  11. 11. The method of claim 1, wherein in the second step, the deposition thickness of the protective material layer is 50 to 150A.
  12. 12. The method of claim 1, wherein in the third step, the etching is a full back etching process without using a photomask, the full back etching process removes a portion of the protective material layer, and the protective sidewall is only reserved on an outer sidewall of the first sidewall.
  13. 13. The method of claim 3, wherein the floating gate conductive layer, the control gate conductive layer, the word line conductive layer, and the logic region conductive layer each comprise polysilicon.

Description

Method for improving flash memory reliability Technical Field The present invention relates to the field of integrated circuit manufacturing, and in particular, to a method for improving the reliability of a flash memory. Background In embedded Flash memory, particularly advanced Nord Flash manufacturing processes, the structural morphology of the memory Cell (Cell) is critical to device yield and reliability. Existing Nord Flash memory cells are typically fabricated using a self-aligned process flow. The forming process generally comprises the steps of sequentially forming a stacked structure comprising a floating gate polysilicon layer, an inter-electrode dielectric layer, a control gate polysilicon layer and a hard mask layer on a substrate, opening an opening through the patterned hard mask layer, forming a first side wall on the side wall of the opening, etching the control gate polysilicon layer by taking the hard mask layer and the first side wall as masks, forming a second side wall, etching the floating gate polysilicon layer by utilizing the second side wall, forming a tunneling dielectric layer, filling a word line polysilicon layer, forming a protective cap layer and removing the hard mask layer. After the fabrication of the above-described base structure is completed, a photolithography, etching and Wet photoresist removal (Wet Strip) process of a control gate/control layer (CGCT) is generally required in order to form a circuit connection pattern. However, the following technical problems exist in the existing process flow: during wet photoresist removal or cleaning in the CGCT step, the cleaning solution may undercut (undercut) the exposed first sidewall, resulting in shrinkage of the first sidewall. The recessing of the first sidewall may cause a recess to form between the Control Gate (CG) top and the adjacent structure. When the material (typically silicon nitride) of the subsequent sidewall (Spacer 1) is deposited subsequently, the deposited layer fills the recess, resulting in the subsequent sidewall growing attached to the retracted topography where the local thickness is thinner and the inclination is too great. In the subsequent side wall etching step, the too thin side wall at the concave part of the top angle of the control gate is extremely easy to be etched through or even completely cut off. Once the sidewall is cut, a metal material in a Bit Line Contact (BL CT) formed later may directly Contact the control gate through the sidewall notch, resulting in a Bridge (Bridge) short circuit between the BL CT and the CG. The performance of the Flash device is seriously affected by the short circuit, and the reliability and yield of the product are reduced. Therefore, a new process method is needed to solve the problem of shrinkage of the side wall, improve the morphology of the subsequent side wall, and eliminate the risk of short circuit. Disclosure of Invention The invention provides a method for improving the reliability of a flash memory, which aims to solve the problem that the side wall of a flash memory storage unit is easy to shrink in a wet etching or cleaning process in the prior art, so that the side wall is broken in a subsequent formation, and the short circuit between a control gate and a contact hole is caused. The invention provides a method for improving the reliability of a flash memory, which comprises the following steps: Step one, providing a semiconductor substrate, wherein a memory cell structure is manufactured on the semiconductor substrate; Depositing a protective material layer on the surface of the semiconductor substrate and the memory cell structure; etching the protective material layer, removing the protective material layer on the flat surface, and reserving the protective material layer on the side wall of the storage unit structure to form a protective side wall; Removing the exposed control gate conductive layer and the floating gate conductive layer below the exposed control gate conductive layer by adopting a wet etching process, wherein the protection side wall is used for protecting the memory cell structure from being damaged by etching of the wet etching process; And fifthly, forming a subsequent side wall structure on the semiconductor substrate. Preferably, in the first step, the manufacturing method of the memory cell structure includes sequentially forming a dielectric layer, a floating gate conductive layer, an inter-electrode dielectric layer, a control gate conductive layer and a hard mask layer on a semiconductor substrate, patterning the hard mask layer for opening an opening, forming a first side wall on the side wall of the opening, etching the exposed control gate conductive layer by taking the hard mask layer and the first side wall as masks, forming a second side wall, etching the exposed floating gate conductive layer by taking the second side wall as masks to limit the floating gate structure, forming a tunneling dielectric layer