CN-122028425-A - Method for manufacturing flash memory device

Abstract

The application provides a preparation method of a flash memory device, which is characterized in that in the process of etching a stacked film layer of a storage area to form a first groove and a second groove, a stacked liner oxide layer, a floating gate material layer, an ONO film layer, a control gate material layer, a first dielectric layer and a polysilicon material layer of a lead-out area are not opened, then the entire polysilicon material layer, the first dielectric layer and a second dielectric layer with partial thickness of the lead-out area are etched and removed, finally, while a flash memory unit is defined by etching the polysilicon material layer in the first groove and the second groove of the storage area, the control gate material layer and the ONO film layer of the lead-out area, which define the position of a third groove, are etched.

Inventors

• LIANG XUANMING
• WANG HUI
• ZHOU YANG

Assignees

• 华虹半导体(无锡)有限公司

Dates

Publication Date

20260512

Application Date

20260129

Claims (9)

1. 1. A method of manufacturing a flash memory device, comprising: Providing a substrate, wherein the substrate comprises a storage area and an extraction area which is positioned at the outer side of the storage area and connected with the storage area, a stacked liner oxide layer, a floating gate material layer, an ONO film layer, a control gate material layer and a first dielectric layer are formed on the substrate of the storage area, a first groove and a second groove are formed in the first dielectric layer, the control gate material layer, the ONO film layer and the floating gate material layer, a first side wall structure is covered on the side wall of the first groove, a polysilicon material layer is also filled in the first groove and the second groove, the upper surface of the first dielectric layer is also covered with the polysilicon material layer, and the stacked liner oxide layer, the floating gate material layer, the ONO film layer, the control gate material layer, the first dielectric layer and the polysilicon material layer are formed on the substrate of the extraction area; removing the polysilicon material layer exceeding the upper surface of the first dielectric layer in the storage area and the extraction area; Forming a second dielectric layer, wherein the second dielectric layer covers the first dielectric layer and the polysilicon material layers in the first groove and the second groove of the residual thickness of the storage area, and covers the first dielectric layer of the lead-out area; Etching to remove the second dielectric layer and the first dielectric layer with partial thickness of the lead-out area; Etching the second dielectric layer and the partial thickness of the polysilicon material layer at the top end of the second trench of the storage area, the partial thickness of the second sidewall structure close to the second trench and the partial thickness of the first dielectric layer with a certain width to form a plurality of first openings in the storage area; And etching to remove the residual thickness of the polysilicon material layer in the second groove of the storage area, and etching to remove the residual thickness of the control gate material layer and the ONO film layer at the bottom of the second opening of the extraction area so as to form a third groove in the extraction area.
2. 2. The method for manufacturing a flash memory device according to claim 1, wherein the second dielectric layer and a portion of the thickness of the first dielectric layer of the lead-out area are etched and removed by a wet etching process.
3. 3. The method of manufacturing a flash memory device of claim 1, wherein after etching to remove the second dielectric layer and a portion of the thickness of the first dielectric layer of the lead-out region, the remaining thickness of the first dielectric layer is no more than 150 angstroms.
4. 4. The method of claim 1, wherein during etching the second dielectric layer and a portion of the polysilicon material layer at the top of the second trench in the storage region, the polysilicon material layer is etched to a thickness of at least 200 a.
5. 5. The method of manufacturing a flash memory device according to claim 1, wherein a selective etching process is used to etch and remove the polysilicon material layer with a residual thickness in the second trench of the storage region, and to etch and remove the control gate material layer and the ONO film layer with a residual thickness at the bottom of the second opening of the extraction region.
6. 6. The method of manufacturing a flash memory device of claim 1, wherein the first dielectric layer is silicon oxide.
7. 7. The method of manufacturing a flash memory device according to claim 1, wherein the second dielectric layer is made of silicon oxide.
8. 8. The method of manufacturing a flash memory device of claim 1, wherein the ONO film layer comprises a bottom silicon oxide layer, a middle silicon nitride layer and a top silicon oxide layer stacked.
9. 9. The method of manufacturing a flash memory device according to claim 1, wherein the second dielectric layer is formed to have a thickness of 50-100 angstroms.

Description

Method for manufacturing flash memory device Technical Field The application relates to the technical field of semiconductor manufacturing, in particular to a preparation method of a flash memory device. Background In a non-volatile (Not-Organized Read Only Memory, NORD) memory, a plurality of spaced trenches are formed in the stacked silicon oxide dielectric layer, control gate material layer and ONO film layer of the lead-out region (FLASH STRAP region) outside the memory, as the stacked silicon oxide dielectric layer, control gate material layer and ONO film layer of the lead-out region are etched open simultaneously with the flash memory cell array of the memory region when the memory region defines a word line/bit line (WL/BL) region. However, after the grooves are formed in the lead-out area, when the silicon oxide dielectric layer on the top of the control gate material layer between the grooves of the lead-out area is removed, the ONO film layer exposed out of the side walls of the grooves is easily etched by mistake, so that the surface of the ONO side is damaged, the appearance of the ONO film layer of the lead-out area is unhealthy, appearance defects appear, and even the yield of the finally formed memory device is affected. Disclosure of Invention The application provides a preparation method of a flash memory device, which can solve the problem that the side surface of an ONO film layer of a lead-out area has morphological defects in the traditional preparation process of the flash memory device. The embodiment of the application provides a preparation method of a flash memory device, which comprises the following steps: Providing a substrate, wherein the substrate comprises a storage area and an extraction area which is positioned at the outer side of the storage area and connected with the storage area, a stacked liner oxide layer, a floating gate material layer, an ONO film layer, a control gate material layer and a first dielectric layer are formed on the substrate of the storage area, a first groove and a second groove are formed in the first dielectric layer, the control gate material layer, the ONO film layer and the floating gate material layer, a first side wall structure is covered on the side wall of the first groove, a polysilicon material layer is also filled in the first groove and the second groove, the upper surface of the first dielectric layer is also covered with the polysilicon material layer, and the stacked liner oxide layer, the floating gate material layer, the ONO film layer, the control gate material layer, the first dielectric layer and the polysilicon material layer are formed on the substrate of the extraction area; removing the polysilicon material layer exceeding the upper surface of the first dielectric layer in the storage area and the extraction area; Forming a second dielectric layer, wherein the second dielectric layer covers the first dielectric layer and the polysilicon material layers in the first groove and the second groove of the residual thickness of the storage area, and covers the first dielectric layer of the lead-out area; Etching to remove the second dielectric layer and the first dielectric layer with partial thickness of the lead-out area; Etching the second dielectric layer and the partial thickness of the polysilicon material layer at the top end of the second trench of the storage area, the partial thickness of the second sidewall structure close to the second trench and the partial thickness of the first dielectric layer with a certain width to form a plurality of first openings in the storage area; And etching to remove the residual thickness of the polysilicon material layer in the second groove of the storage area, and etching to remove the residual thickness of the control gate material layer and the ONO film layer at the bottom of the second opening of the extraction area so as to form a third groove in the extraction area. Optionally, in the method for manufacturing the flash memory device, a wet etching process is used to etch and remove the second dielectric layer of the lead-out area and the first dielectric layer with partial thickness. Optionally, in the method for manufacturing the flash memory device, after etching to remove the second dielectric layer and the first dielectric layer with partial thickness of the lead-out area, the remaining thickness of the first dielectric layer is not more than 150 angstroms. Optionally, in the method for manufacturing the flash memory device, the thickness of the polysilicon material layer etched and removed is at least 200 angstroms in the process of etching the second dielectric layer at the top end of the second trench of the storage region and the polysilicon material layer with a partial thickness. Optionally, in the method for manufacturing the flash memory device, a selective etching process is adopted to etch and remove the polysilicon material layer with the residual thickness in th