CN-122028426-A - Floating gate type split gate flash memory in CMOS process and manufacturing method

Abstract

The invention discloses a floating gate type split gate flash memory and a manufacturing method thereof in a CMOS (complementary metal oxide semiconductor) process, wherein a semiconductor substrate comprises a storage unit area and a logic area, the storage unit comprises a selection tube and storage tubes which are symmetrically arranged at two sides of the selection tube, the selection gate of the selection tube is formed in a groove type space formed by a first side wall and a second side wall, a control gate and an ONO (oxide-nitride-oxide) layer are arranged below the first side wall, a floating gate and a floating gate dielectric layer are arranged below the second side wall, a third side wall is arranged at the outer side of the first side wall, and the third side wall is arranged above the floating gate. The length of the control gate and the length of the ONO layer can be adjusted by controlling the thickness of the first side wall, a third side wall compatible with a CMOS process is arranged on the outer sides of the control gate and the ONO layer, LDD with floating gate polycrystalline silicon injection is adopted, the LDD injection is placed before the outer side of the floating gate is etched, the overlapping area of the LDD and the floating gate is increased under the condition that the LDD energy is not increased, the second etching of the outer side floating gate is shared with the gate etching of the CMOS device, and the process manufacturing compatibility is improved.

Inventors

• XU ZHAOZHAO
• GUO YUHANG
• ZHANG YINTONG
• LIU DONGHUA

Assignees

• 华虹半导体(无锡)有限公司
• 上海华虹宏力半导体制造有限公司

Dates

Publication Date

20260512

Application Date

20260130

Claims (15)

1. 1. A manufacturing method of a floating gate split gate flash memory in a CMOS process is characterized in that: Providing a semiconductor substrate of a first conductivity type, and planning a storage area of a flash memory device and a CMOS logic area on the semiconductor substrate; For the storage area, growing a floating gate oxide layer on a semiconductor substrate of a first conductivity type, and then sequentially growing a floating gate polysilicon layer and a first silicon nitride layer; for the CMOS logic area, keeping consistent with the storage area process; sequentially depositing an ONO layer, a control gate polysilicon layer and a second silicon nitride layer among the polysilicon, photoetching to define a flash memory cell area, and etching to remove the silicon nitride layer in the opening area; The CMOS logic is not turned on; The third step, depositing a silicon oxide layer and etching to form a first side wall, using the first side wall as a hard mask to anisotropically etch the control gate polysilicon layer to form a self-aligned control gate, etching the ONO layer, depositing an insulating dielectric layer and etching to form a second side wall, using the second side wall and the first side wall together as a hard mask to form a floating gate by self-aligned etching, sequentially depositing a select gate dielectric layer and a select gate polysilicon layer to form a self-aligned select gate, and forming a protective oxide layer on the top of the select gate; the CMOS logic area is not opened under the protection of the hard mask, and is not patterned; Fourthly, coating photoresist, developing, opening a Cell region, covering the CMOS region by the photoresist, taking the first side wall, the selective gate dielectric layer and the protective oxide layer as hard masks, etching and removing the second silicon nitride layer remained outside the first side wall, and then sequentially etching the control gate polysilicon layer and the ONO layer to expose the floating gate polysilicon layer; For the CMOS logic region, before removing the hard mask of the Cell region, defining the CMOS region by photoetching, taking photoresist as a mask to selectively etch and remove the hard mask, the control gate polysilicon layer, the ONO layer, the floating gate polysilicon layer and the floating gate oxide layer of the CMOS region in sequence, and injecting the hard mask, the control gate polysilicon layer, the ONO layer, the floating gate polysilicon layer and the floating gate oxide layer to form a CMOS well; Fifthly, depositing a hard mask dielectric layer for CMOS gate etching to cover the storage area; The hard mask medium layer of the CMOS logic area is synchronously covered; Step six, coating and developing photoresist, opening a Cell region, covering a CMOS grid by the photoresist, and sequentially etching a hard mask dielectric layer of the CMOS region to form a third side wall; for the CMOS logic region, synchronously etching the polysilicon layer of the CMOS logic region to form a grid electrode of the CMOS logic region when etching the third side wall of the storage region; A seventh step of depositing a dielectric layer, etching the outer layer of the third side wall in the storage area, forming a fourth side wall, and synchronously forming a first side wall of the CMOS logic area of the grid electrode in the CMOS logic area; The eighth step, the storage area is covered by photoresist, the CMOS logic area is opened, and ion implantation and halo implantation are carried out by taking the first side wall and the gate of the CMOS logic area as hard masks, so as to form LDD of the CMOS logic area; and a ninth step of depositing a dielectric layer and etching to form a fifth side wall of the storage area, etching to form a second side wall of the CMOS logic area synchronously, and forming a source area and a drain area by synchronous ion implantation of the storage area and the CMOS logic area.
2. 2. The method for manufacturing the floating gate split gate flash memory in the CMOS process of claim 1, wherein the method comprises the following steps: the semiconductor substrate is a silicon substrate or a compound semiconductor.
3. 3. The method of manufacturing a floating gate split gate flash memory in a CMOS process as claimed in claim 1, wherein in the first step, a floating gate oxide layer is formed on a surface of a semiconductor substrate by a thermal oxidation method; The first silicon nitride layer is used as a hard mask layer for STI etching, the first silicon nitride layer is removed after the STI etching is completed, and the subsequent storage units are completed in an active region defined between the STI.
4. 4. The method of manufacturing a floating gate split gate flash memory in a CMOS process of claim 1, wherein in the third step, a first sidewall is formed after etching the silicon oxide layer, and the width of the bottom of the first sidewall defines the length of the control gate; The etching of the second side wall is anisotropic etching; The space between the second side walls defines a formation area of the selection gate; After the selective gate polysilicon layer is deposited, a selective gate is formed by utilizing a CMP process, and then a protective oxide layer is formed on the top of the selective gate by utilizing a thermal oxidation method to cover the selective gate.
5. 5. The method of claim 1, wherein in the third step, the second sidewall is made of silicon oxide.
6. 6. The method of claim 1, wherein in the third step, the material of the select gate dielectric layer is silicon oxide, and the select gate dielectric layer is formed by thermal oxidation.
7. 7. The method of manufacturing a floating gate split gate flash memory in a CMOS process according to claim 1, wherein in the fourth step, the control gate polysilicon and the ONO layer are etched by using the first sidewall as a hard mask for the storage region until the floating gate polysilicon layer is exposed, thereby forming the control gate of the storage region; and forming LDD by ion implantation through the floating gate polysilicon, and placing the LDD implantation before etching outside the floating gate, so that the overlapping area of the LDD and the floating gate can be increased without increasing the energy of the LDD.
8. 8. The method of claim 1, wherein in the sixth step, the hard mask dielectric layer is a silicon oxide layer; and etching the hard mask dielectric layer and the floating gate polysilicon layer of the storage area during the etching process of the grid electrode of the CMOS logic area, so as to improve the process compatibility.
9. 9. A floating gate split gate flash memory in a CMOS process is characterized by comprising the following components: the semiconductor substrate comprises a memory cell area and a logic area, wherein the memory cell area is formed by an array formed by memory cells; the storage unit comprises a selection tube and storage tubes which are symmetrically arranged at two sides of the selection tube; The selection gate of the selection tube is formed in a groove-shaped space formed by the first side wall and the second side wall; the floating gate and floating gate dielectric layer are arranged below the second side wall, and the second side wall is positioned at the inner side of the first side wall; And a third side wall is arranged on the outer side of the first side wall and is positioned on the floating gate.
10. 10. The floating gate split gate flash memory of claim 10, wherein a select gate dielectric layer is disposed between said select gate and said first and second sidewalls.
11. 11. The floating gate split gate flash memory of claim 10, wherein the thickness of the bottom of the first sidewall determines the length of the control gate.
12. 12. The floating gate split gate flash memory of claim 10, wherein said third sidewall dielectric layer is compatible with CMOS process.
13. 13. The floating gate split gate flash memory of claim 10, wherein the third sidewall comprises a storage region fourth sidewall and a storage region fifth sidewall, and the first sidewall and the second sidewall of the CMOS logic region are simultaneously formed by etching the storage region fourth sidewall and the storage region fifth sidewall.
14. 14. The floating gate type split gate flash memory of claim 10, wherein said semiconductor substrate further comprises LDD regions and source and drain regions of memory cells and source and drain regions of CMOS logic regions.
15. 15. The floating gate split gate flash memory of claim 10, wherein said select gate has a protective oxide layer on top.

Description

Floating gate type split gate flash memory in CMOS process and manufacturing method Technical Field The invention relates to the field of semiconductor device manufacturing processes, in particular to a floating gate split gate flash memory in a CMOS process. Background Floating-gate (split-gate) flash memory technology is widely used in applications of various embedded electronic products such as financial IC cards, automotive electronics, and the like. The memory integration density is improved, so that the chip area is saved, and the manufacturing cost is reduced. The structure of the conventional split gate floating gate flash memory of 2-bit/cell (two bits per memory cell) is shown in the left side of fig. 7, and includes a middle selection tube and memory tubes which are positioned on both sides of the selection tube and are bilaterally symmetrical, so that a 2-bit memory cell is formed. The manufacturing flow is shown in fig. 1-7, wherein the left side of the synchronous process in each figure is a storage area, and the right side is a CMOS logic area: in the first step, a floating gate oxide layer 102 is grown on a P-type substrate by thermal oxidation, a polysilicon (Poly) layer 103 and a silicon nitride layer 502 are grown, the silicon nitride layer 502 is used as a hard mask layer for etching, and an STI (shallow-trench-isolation) 501 process is performed to define an active region of a memory region and a peripheral logic region, as shown in the left side of fig. 1. The CMOS logic region on the right in fig. 1 is consistent with the memory region on the left. And removing the silicon nitride layer 502, sequentially depositing the inter-polysilicon ONO layer 104, the floating gate polysilicon layer 105 and the thick silicon nitride layer 503, photoetching to define a flash memory storage unit area, and etching to remove the silicon nitride layer 503 in the opening area, as shown in the left side of FIG. 2. The CMOS logic region on the right in fig. 2 is not open. Third, a silicon oxide layer is deposited, and anisotropic etching is used to form a first sidewall dielectric layer 113, where the bottom width of the sidewall defines the length of the control gate. The control gate polysilicon is anisotropically etched using the first sidewall as a hard mask to form a self-aligned control gate (polysilicon under the first sidewall 113) and to etch the underlying ONO layer 104. And forming a floating gate (composed of polysilicon below the second side wall 106) by self-aligned etching by using the second side wall and the first side wall together as a hard mask. A select gate dielectric layer 107 and a select gate polysilicon layer 108 are deposited in sequence. And self-aligned select gates 108 within the trenches are formed by CMP. Thermal oxidation forms silicon oxide 114 over 108. Resulting as shown on the left side of fig. 3. The CMOS logic area on the right in fig. 3 is unchanged. In the fourth step, the first sidewall 113, the select gate dielectric layer 107, and the protective oxide layer 114 are used as hard masks, and the second silicon nitride layer 503 remaining on both sides is etched away, so as to form a structure as shown in the left side of fig. 4. As for the CMOS logic region on the right side, before removing the second silicon nitride layer 503, a CMOS region is defined by photolithography, the second silicon nitride layers 503, 105, 104, 103, 102 of the CMOS region are etched sequentially by using the photoresist 504 as a mask, wells 201 of the CMOS region are formed by injection, a CMOS gate dielectric layer 202 is formed by thermal oxidation, a CMOS polysilicon 203 is formed by deposition and a CMOS gate is formed by selective etching, and the right side of fig. 4 is formed. Fifth, the first sidewall 113, the select gate dielectric layer 107, and the protection oxide layer 114 are used as hard masks (while the CMOS region is covered with photoresist 504), the control gate polysilicon 105, the ONO layer 104, and the floating gate polysilicon 103 remaining on both sides are removed, and ion implantation is sequentially performed to form LDD109, so as to form LDD109 as shown in the left side of fig. 5. As for the CMOS logic region, it is capped with photoresist 504, which is formed as shown on the right side of fig. 5. In the sixth step, a dielectric layer is deposited and etched to form a third sidewall 110 (i.e., the first sidewall of the right CMOS device), as shown in the left side of fig. 6. For the CMOS region, a first side wall 110 of the CMOS (i.e. a third side wall of the left flash memory device) is also deposited and etched, the CMOS region is opened by photoetching, and LDD/Halo of the CMOS device is self-aligned to form a CMOS LDD region 209 by taking 203 and 110 as masks, as shown on the right side of FIG. 6. Seventh, a storage region fourth sidewall 111 (i.e., the second sidewall of the CMOS device) is deposited and etched, and a source drain implant is formed 112, w